Hiroki Yonemitsu

Contact hole shrink process using graphoepitaxial directed self-assembly lithography

Abstract. A contact hole shrink process using directed self-assembly lithography (DSAL) for sub-30 nm contact hole patterning is reported on. DSAL using graphoepitaxy and poly (styrene-block-methyl methacrylate) (PS-b-PMMA) a block copolymer (BCP) was demonstrated and characteristics of our process are spin-on-carbon prepattern and wet development. Feasibility of DSAL for semiconductor device manufacturing was investigated in terms of DSAL process window. Wet development process was optimized first; then critical dimension (CD) tolerance of prepattern was evaluated from three different aspects, which are DSA hole CD, contact edge roughness (CER), and hole open yield. Within 70+/−5  nm hole prepattern CD, 99.3% hole open yield was obtained and CD tolerance was 10 nm. Matching between polymer size and prepattern size is critical, because thick PS residual layer appears at the hole bottom when the prepattern holes are too small or too large and results in missing holes after pattern transfer. We verified the DSAL process on a 300-mm wafer at target prepattern CD and succeeded in patterning sub-30 nm holes on center, middle, and edge of wafer. Average prepattern CD of 72 nm could be shrunk uniformly to DSA hole pattern of 28.5 nm. By the DSAL process, CD uniformity was greatly improved from 7.6 to 1.4 nm, and CER was also improved from 3.9 to 0.73 nm. Those values represent typical DSAL rectification characteristics and are significant for semiconductor manufacturing. It is clearly demonstrated that the contact hole shrink using DSAL is a promising patterning method for next-generation lithography.

Novel error mode analysis method for graphoepitaxial directed self-assembly lithography based on the dissipative particle dynamics method

Directed self-assembly lithography (DSAL), which combines self-assembling materials and a lithographically defined prepattern, is a potential candidate to extend optical lithography beyond 22 nm. To take full advantage of DSAL requires diminishing not only systematic error modes but also random error modes by carefully designing a lithographically defined prepattern and precisely adjusting process conditions. To accomplish this with satisfactory accuracy, we have proposed a novel method to evaluate DSAL error modes based on simulations using dissipative particle dynamics (DPD). We have found that we can estimate not only systematic errors but also random errors qualitatively by simulations.

Dissipative particle dynamics simulations to optimize contact hole shrink process using graphoepitaxial directed self-assembly

Dissipative particle dynamics (DPD) simulations are utilized to optimize contact hole shrink process using graphoepitaxial directed self-assembly (DSA). In this work, poly (styrene-block-methyl methacrylate) (PS-b-PMMA) was employed. In the contact hole shrink process, PS residual layer was formed on the bottom floor of the hole type prepattern. To realize reliable contact hole shrink process, minimization of the thickness of PS residual layer was one of the key issues. It was found that the minimization of the thickness of the PS residual layer and optimization of threedimensional configuration of the PMMA domain was trade-off relationship. By using DPD simulations, the parameters were successfully optimized to achieve residual layer free contact hole shrink of DSA lithography.

Contact hole shrink process using directed self-assembly

We report on a contact hole shrink process using directed self-assembly. A diblock copolymer, poly (styrene-blockmethyl methacrylate) (PS-b-PMMA), is used to shrink contact holes. Contact hole guide patterns for graphoepitaxy are formed by ArF photoresists. Cylindrical domains of PMMA is removed using organic solvents after DUV (λ <200 nm) irradiation. In this work, it is found that a solvent system is the best developer from the evaluated single solvent systems and mixed solvent systems. The wet development of PS-b-PMMA strongly depends on total exposure dose of DUV irradiation. With lower exposure dose, the cylindrical domains of PMMA are not clearly removed. With optimum exposure dose, PMMA is developed clearly. The contact hole guide patterns of 75 nm in diameter are successfully shrunk to 20 nm in diameter using the wet development process.

Metrology and inspection required for next generation lithography

We summarize the metrology and inspection required for the development of nanoimprint lithography (NIL) and directed self-assembly (DSA), which are recognized as candidates for next generation lithography. For NIL, template inspection and residual layer thickness (RLT) metrology are discussed. An optical-based inspection tool for replica template inspection showed sensitivity for defects below 10 nm with sufficient throughput. Scatterometry was applied for RLT metrology. Feedback control with scatterometry improved RLT uniformity across an imprinting field. For DSA, metrology for image placement and cross-sectional profile are addressed. Design-based scanning electron microscope (SEM) metrology utilizing a die-to-database electron beam (EB) inspection tool was effective for image placement metrology. For the cross-sectional profile, a holistic approach combining scatterometry and critical dimension SEM was developed. The technologies discussed here will be important when NIL and DSA are applied for IC manufacturing, as well as in the development phases of those lithography technologies.

Immersion resist process for 32-nm node logic devices

Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The target of reflectivity control over existent substrate thickness variation is 0.4%, which was estimated from our dose budget analysis. Then, single BARC process or stacked mask process (SMAP) was selected to each of the critical layers according to the substrate transparency. Another key issue in terms of material process was described in this paper, that is spin-on-carbon (SOC) pattern deformation during substrate etch process. New SOC material without any deformation during etch process was successfully developed for 32nm node stacked mask process (SMAP). 1.3NA immersion lithography and pattern transfer performance using single BARC

Feasibility of Ultra-Low k1 Lithography for 28nm CMOS Node

We have designed the lithography process for 28nm node logic devices using 1.35NA scanner. In the 28nm node, we face on the ultra-low k1 lithography in which dense pattern is affected by the mask topography effect and the oblique-incidence. Using the rigorous lithography simulation considering the electro-magnetic field, we have estimated accurately the feasibility of resolution of the minimum pitch required in 28nm node. The optimum mask plate and illumination conditions have been decided by simulation. The experimental results for 28nm node show that the minimum pitch patterns and minimum SRAM cell are clearly resolved by single exposure.

Resist process control for 32-nm logic node and beyond with NA > 1.30 immersion exposure tool

Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dimensional (2D) layout pattern deformation becomes more severe with stronger RET (e.g., narrow angle CQUAD illumination). Also pattern collapse more frequently happens in 2D-pattern layouts when stronger RET is used. In contrast, milder RET (annular illumination) does not induce the severe pattern collapse in 2D-pattern layout. For 2D-pattern layouts, stronger RET seems to worsen image contrast and results in high background-light in the resist pattern, which induces more pattern collapse. For the minimum-pitch L/S pattern in 32-nm node logic, annular illumination is acceptable for patterning with NA1.35 scanner when high contrast resist is used. For contact/via patterns, it is necessary to expand the overlapping CD process window. Better process margin is realized through the combination of hole-shrink technique and precise acid-diffusion control in an ArF chemically amplified resist.