Hiromasa Noda

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAMs is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.

Simulation of sub-0.1- mu m MOSFETs with completely suppressed short-channel effect

MOSFETs in the sub-0.1- mu m regime were investigated using a nonplanar device simulator CADDETH-NP. It was found that even in this regime, the short-channel effect can be suppressed in grooved gate MOSFETs because of the concave corner of the gate insulator. MOSFETs with a gate length of 0.05 mu m or less with no threshold voltage lowering can be made by optimizing the concave corner radius, junction depths, and channel doping.<<ETX>>

Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate

Grooved-gate Si MOSFETs with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 /spl mu/m. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 /spl mu/m between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-/spl mu/m source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects. >

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8:4 Multiplexed Data-Transfer Scheme

Three circuit techniques for an 8.1-ns column-access 1.6-Gb/s/pin 512-Mb DDR3 SDRAM using 90-nm dual-gate CMOS technology were developed. First, an 8:4 multiplexed data-transfer scheme, which operates in a quasi-4-bit prefetch mode, achieves a 3.17-ns reduction in column-access time, i.e., from 11.3 to 8.13 ns. Second, a dual-clock latency counter reduces standby power by 22% and cycle time from 1.7 to 1.2 ns. Third, a multiple-ODT-merged output buffer enables selection of five effective-resistance values Rtt (20, 30, 40, 60, and 120 Omega) without increasing I/O capacitance. Based on these techniques, 1.6-Gb/s/pin operation with a 1.36-V power supply and a column latency of 7 was accomplished

Threshold voltage controlled 0.1-/spl mu/m MOSFET utilizing inversion layer as extreme shallow source/drain

MOSFETs containing sub-gates as sidewall spacers of the main gate are fabricated. The inversion layers induced in these MOSFETs by the sub-gates are used as source and drain, in order to investigate how the extremely shallow junction affects the short channel characteristics of MOSFETs. Significant improvement in the short channel characteristics is observed in comparison with conventional MOSFETs whose junctions are formed by ion implantation. These new MOSFETs do not show threshold voltage roll-off at the defined gate length around 0.1 /spl mu/m, and punchthrough is not observed down to 0.07 /spl mu/m.<<ETX>>

A sub-0.1-/spl mu/m grooved gate MOSFET with high immunity to short-channel effects

Grooved gate MOSFETs in the sub-0.1-/spl mu/m regime have been studied by both experiments and simulations. Phase-shifted lithography was used to realize sub-0.1-/spl mu/m gate length. The fabricated device shows no threshold voltage roll-off into sub-0.1-/spl mu/m regime. The effects of the grooved gate structures are investigated using a nonplanar device simulator, and the optimization of the groove corner shape is found to be important to obtain high device performance.<<ETX>>

A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography

Summary form only given. A novel 0.1- mu m-gate elevated source and drain MOSFET was fabricated utilizing phase-shifted lithography. Phase-shifted lithography enabled less than 0.2- mu m spacing, resulting in a 0.1- mu m gate length in combination with a side-wall oxide film formation technique. It is concluded that the new gate definition process utilizing phase-shifted lithography will be promising for future ultrasmall device fabrication.<<ETX>>

Tungsten Gate Technology for Quarter-Micron Application.

The feasibility of pure tungsten as a gate electrode of quarter-micron MOSFETs (metal-oxide-semiconductor field effect transistors) was investigated experimentally. Issues investigated are 1) tungsten gate dry etching, 2) gate oxide dielectric for the tungsten gate, and 3) threshold voltage control of tungsten gate MOSFET. A 0.1-µm tungsten gate electrode on a 5-nm-thick gate oxide was fabricated successfully for the first time, using microwave plasma etching and chlorine as the reaction gas. It was confirmed that the dielectric characteristics of the gate oxide for the tungsten gate are acceptable when its thickness exceeds 6 nm. It was demonstrated that the threshold voltage of tungsten gate MOSFETs was successfully controlled by counter-doping without degradation of the short-channel characteristics.

Short channel characteristics of Si MOSFET with extremely shallow source and drain regions formed by inversion layers

The influence of extremely shallow source and drain junctions on the short channel effects of Si MOSFETs are experimentally investigated. These extremely shallow junctions are realized in MOSFETs with a triple-gate structure. Two subgates formed as side-wall spacers of a main gate induce inversion layers which work as the virtual source and drain. Significant improvement in threshold voltage roll-off and punchthrough characteristics are obtained in comparison with conventional MOSFETs whose junctions are formed by ion implantation: threshold voltage roll off is suppressed down to a physical gate length of 0.1 /spl mu/m while punchthrough is suppressed down to 0.07 /spl mu/m, the minimum pattern size delineated. It is also demonstrated experimentally that the carrier concentrations in the source and drain do not have any influence on the short channel effects. >

An on-chip clock-adjusting circuit with sub-100-ps resolution for a high-speed DRAM interface

A novel fully digital fine-delay circuit for a high-speed DRAM interface is proposed. The circuit consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-/spl mu/m technology demonstrates that a resolution of 26 ps can be achieved. A clock-recovery circuit using this circuit has a two-clock-cycle lock time and sub-100-ps error.