Youji Idei

Dual-period self-refresh scheme for low-power DRAM's with on-chip PROM mode register

A dual-period self-refresh (DPS-refresh) scheme for low-power DRAMs is proposed. Word lines are classified into two groups according to retention test data which are stored in a PROM mode register implemented in the chip periphery. The word lines are controlled individually by combining the memory-mat-select signal and the classification signal from the PROM register. The effective refresh period can be extended by four to six times compared to the conventional self-refresh period. Data-retention current of a 64-Mb DRAM test chip featuring the proposed DPS-refresh scheme is reduced to half the conventional self-refresh current without considerable area penalty.

Soft-error characteristics in bipolar memory cells with small critical charge

The alpha-particle-induced soft-error mechanism in a high-speed bipolar static RAM (SRAM) which is used for mainframe computers is investigated using a three-dimensional (3-D) device and a circuit simulator. It is shown that a constant critical charge for the memory cell does not exist. This is because the memory cells soft-error sensitivities to the charges collected at the base and collector of the cell transistor are different due to the difference in time constants of the base and collector. To take into account this sensitivity difference in the soft-error rate simulation, an effective-charge model is proposed. This model incorporates weight coefficients that express the memory cells soft-error sensitivities to the charges collected at the base and collector. Accelerated soft-error rates of the 4-kb SRAMs are simulated using the effective-charge model. >

High-speed sensing techniques for ultrahigh-speed SRAMs

Two high-speed sensing techniques suitable for ultrahigh-speed SRAMs are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAMs. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAMs for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of that of conventional cells. A 64-kb SRAM fabricated with one of the sensing techniques using 0.5- mu m BiCMOS technology achieved a 1.5-ns access time with a 78- mu m/sup 2/ memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAMs, which have been used as cache and control memories of mainframe computers. >

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-/spl mu/m/sup 2/ memory cells has been developed using 0.3-/spl mu/m BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAMs, which have been used as cache and control storages in mainframe computers. >

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM

A 1.5-ns access time, 78- mu m/sup 2/ memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers. >

Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise; a critical damping emitter follower for the overshoot noise; and a twisted-bit line structure with a normally on equalizer for the bit line crosstalk. The authors describe the noise generation mechanisms and the operation of circuits using each of the techniques. Experimental results are also described.<<ETX>>

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry

A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed.