K. T. Park

Three-dimensional shared memory fabricated using wafer stacking technology

We proposed a new three-dimensional (3D) shared memory for a high performance parallel processor system. In order to realize such new 3D shared memory, we have developed a new 3D integration technology based on the wafer stacking method. We fabricated the 3D shared memory test chip with three memory layers using our 3D integration technology. It was demonstrated that the basic memory operation and the broadcast operation of 3D shared memory are successfully performed.

Intelligent image sensor chip with three dimensional structure

A new three-dimensional (3D) integration technology based on wafer bonding technique has been proposed for intelligent image sensor chip with 3D stacked structure. We have developed key technologies for such 3D integration. A 3D image sensor test chip was fabricated using this 3D integration technology. Basic electric characteristics were evaluated in the 3D image sensor test chip.

Development of Three-Dimensional Integration Technology for Highly Parallel Image-Processing Chip

A new three-dimensional (3D) integration technology for realizing a highly parallel image-processing chip has been developed. Several LSI wafers are vertically stacked and glued to each other after thinning them using this new technology. This technology can be considered as both 3D LSI technology and wafer-scale 3D chip-on-chip packaging technology. The effective packaging density can be significantly increased by stacking the chips in a vertical direction. Several key techniques for this 3D integration have been developed. In this paper, we demonstrate the highly parallel image sensor chip with a 3D structure. The 3D image sensor test chip was fabricated using this new 3D integration technology and its basic performance was evaluated.

Filling of Tungsten into Deep Trench Using Time-Modulation CVD Method

Y. Igarashi, T. Morooka, Y. Yamada, T. Nakamura, K.W. Leel, ICT. park, H. Kurino and M. Koyanagr DepL ofMachine lntelligence and Systems Engineering, Ibhoku Univ. 0l Aza-Ararnaki, Aoba-ku, Sendei 98G8579, Japan Phone: +81-22-217{909; E-Mail: sdlab(Asd.mech.tohoku.acjp rJST(Japan Science and Technolo

New Silicon-on-Insulator (SOI) Flash Memory with Side Channel and Side Floating Gate

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A 3-Dimensional Wafer-Level Stacking Technology with Precise Vertical Interconnections to MEMS Applications

A new silicon-on-insulator (SOI) flash memory with a side channel and side floating gate has been proposed to reduce the power consumption and to increase the packing density in this paper. We utilized atomic layer doping (ALD) method for forming the ultra shallow junction on the side surface of the device. The threshold voltage shift of 0.25 V was obtained for small erasing/writing voltages in a 0.1 µm SOI flash memory. This device can be operated with a small number of electrons.

Three-Dimensional Integration of Fully Depleted SOI Devices

This paper presents a wafer-level stacking technology with vertical interconnections for 3-dimensional (3-D) microsystems. Several thinned chips, which are composed of homo or heterogeneous devices and systems, are vertically stacked and electrically interconnected with more than 105 precise and short vertical wires formed through the chips. Deep Si trench-holes filled with low-resistance P-doped poly-Si and Au/In micro-bumps were used for the vertical interconnections between chips. An 8×8 pixels 3-D stacked CMOS image sensor was fabricated and successfully demonstrated its functions.

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology

L.Intmduction Recently, threedimensional (3D) integration technology has attracted much attention since it offers the possibility of solving tlre serious interconnection problems in funre LSIs. To rffilva high-performance and highly parallel processing LSIs, we have develo@ a new 3D integration technology using a novel wafer level stacking technique. we fabricated 3D stacked innge sensor and 3D shared rnemory by sacking bulk device wafers I l-2]. However, one of tlre major concems in such 3D LSI with bulk devices is an increase of toal power consurnption. Then, we riod to fabricate 3D LsI by stacking fully depleted sol device wafers in order to reduce the power consumption. Fully depleted SOI devices are very useful to rcduce the power consumption and to increase the speed. Frnthermore, 3D I-

Development of the Three-Dimensional Integration Technology for Highly Parallel Image Processing Chip

with sol devices allow us to dramatically reduce the length of vertical interconnections which elecrically connect an upper layer and a lower layer. This also leads to the decrease of ttre powerconsumption in addition to the increase of speed. In tlris paper, we describe a new 3D infgration trchnology using fully depleted SOI device wafers.