Sang-Youl Lee

Investigation of zinc interstitial ions as the origin of anomalous stress-induced hump in amorphous indium gallium zinc oxide thin film transistors

In this paper, we investigated an anomalous hump in the bottom gate staggered amorphous indium-gallium zinc oxide thin-film transistors. During the positive gate bias stress, a positive threshold voltage shift is observed in transfer curve and an anomalous hump occurs as the stress time increases. The hump becomes more serious as the gate bias stress increases while it is not observed under the negative bias stress. From the simulation of a long range migration of zinc interstitial ions (Zni) and the measurement of the diode characteristics after the constant positive bias stress, the origin of the hump can be explained by the migration of the positively charged mobile Zni during the constant positive gate bias stress, which can be conformed by increasing the concentration of Zni from the result of the Auger ZnL3M4.5M4.5 spectra.

Anomalous Stress-Induced Hump Effects in Amorphous Indium Gallium Zinc Oxide TFTs

In this paper, we investigated the anomalous hump in the bottom gate staggered a-IGZO TFTs. During the positive bias stress, a positive threshold voltage shift was observed in the transfer curve and an anomalous hump occurred as the stress time increased. The hump became more serious in higher gate bias stress while it was not observed under the negative bias stress. The analysis of constant gate bias stress indicated that the anomalous hump was influenced by the migration of positively charged mobile interstitial zinc ion towards the top side of the a-IGZO channel layer.

Investigation of the instability of low-temperature poly-silicon thin film transistors under a negative bias temperature stress

In this work, we analyzed and correlated the hysteresis characteristics and instability under negative bias temperature instability (NBTI) stress in p-channel low-temperature poly-silicon (LTPS) thin-film transistors (TFTs). Positive VTH shifts were observed under the NBTI stress. The hysteresis does not appear to be affected by the NBTI stress; however, when the VG stress voltage is −40 V at 100°C, the hysteresis increases as the stress time increases and VTH shifts with sub-threshold slope (SS) degradation. The hysteresis may increase under the extreme stress condition due to the generation of trap-states.

Electrical Characteristic Analysis of Postannealed ZnO Thin-Film Transistors under O2 Ambient

An electrical characteristic analysis of postannealed ZnO thin-film transistors (TFTs) under O2 ambient from 200 to 300 °C for 1 h was carried out. The 250-°C-annealed device showed the best electrical characteristics, which can be explained by crystallinity improvement on the basis of X-ray diffraction (XRD) analysis. However, although having an active layer of the best crystal quality, the electrical properties of the 300-°C-annealed device were degraded, which can be due to the higher ΦB0 resulting from the oxidation of Ti used as the S/D electrodes. Next, the stability of ZnO TFTs was investigated. Under a positive bias stress of 20 V, it was found that the annealed devices showed smaller threshold voltage shifts (ΔVTH) than the as-grown device. In addition, with the stress bias removed, all devices recover their original characteristics, which can be explained by temporary charge trapping into preexisting traps. Therefore, the post-thermal annealing under O2 ambient can improve the electrical and reliability characteristics of ZnO TFTs, which can be explained by a fewer grain boundary traps and a lower grain boundary potential barrier, as determined by 1/f noise analysis, closely related to the crystallinity improvement of the active layer and fewer zinc interstitials and/or oxygen vacancies near the grain boundary in the active layer.

Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of ion implantation ( I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage () of 0.13 V, and a higher of 18.6 and mobility of 27.02 than the conventional and I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

Investigation of the Gate Bias Stress Instability in ZnO Thin Film Transistors by Low-Frequency Noise Analysis

To investigate the electrical instability mechanism under the application of gate bias stress and relaxation, the 1/f noise spectra of two different ZnO thin-film transistors (TFTs) were analyzed. In terms of gate bias dependence (SIDS/IDS), both devices followed a mobility fluctuation model based on the traps in their channel layers prior to and after stress. Device A (channel thickness: 20 nm), recovered its initial noise parameter (αapp) after relaxation, in exact agreement with the current–voltage (I–V) measurement results; this shows that in device A, the dominant phenomenon under the application of stress was temporary charge trapping at grain boundary traps. However, in device B (channel thickness: 80 nm), αapp did not recover its initial values after relaxation, and transfer parameters, such as VTH, mobility, SS, and Nt, degraded after the gate bias stress. Moreover, after the stress, device B showed a reduced gate insulator breakdown voltage. The electrical degradation seen in device B can be explained by trap creation and/or charge injection near channel/gate oxide interfaces, including those within the channel layer.

Characterization of polycrystalline silicon-oxide-nitride-oxide-silicon devices on a SiO2 or Si3N4 buffer layer

Silicon-oxide-nitride-oxide-silicon (SONOS) memory devices were fabricated from polycrystalline silicon (poly-Si) using the solid phase crystallization (SPC) method for use in a low-power system-on-panel (SOP) display. In these poly-Si SONOS memories, oxide or nitride was used as a buffer layer. The electrical characteristics, such as the threshold voltage (VT), subthreshold slope (SS) and transconductance (gm), were determined for each SONOS device. To interpret the characteristics of both poly-Si devices, x-ray diffraction (XRD) measurements and flicker noise analysis were conducted. The results show that the poly-Si SONOS on the oxide layer has better electrical, memory characteristics, such as turn-on speed and gm, program/erase, endurance and data retention than that on the nitride layer. From the XRD measurements, it is shown that the grain size of the poly-Si on the oxide layer is larger than that on the nitride layer. From the flicker noise analysis, the poly-Si device on oxide was shown to have less traps or defects in the channel layer than that on nitride.

The 1/f Noise Analysis of 3D SONOS Multi Layer Flash Memory Devices Fabricated on Nitride or Oxide Layer

In this paper, we compared and analyzed 3D silicon-oxide-nitride-oxide-silicon (SONOS) multi layer flash memory devices fabricated on nitride or oxide layer, respectively. The device fabricated on nitride layer has inferior electrical properties than that fabricated on oxide layer. However, the device on nitride layer has faster program / erase speed (P/E speed) than that on the oxide layer, although having inferior electrical performance. Afterwards, to find out the reason why the device on nitride has faster P/E speed, 1/f noise analysis of both devices is investigated. From gate bias dependance, both devices follow the mobility fluctuation model which results from the lattice scattering and defects in the channel layer. In addition, the device on nitride with better memory characteristics has higher normalized drain current noise power spectral density (>), which means that it has more traps and defects in the channel layer. The apparent hooge`s noise parameter () to represent the grain boundary trap density and the height of grain boundary potential barrier is considered. The device on nitride has higher values, which can be explained due to more grain boundary traps. Therefore, the reason why the devices on nitride and oxide have a different P/E speed can be explained due to the trapping/de-trapping of free carriers into more grain boundary trap sites in channel layer.

Analysis of An Anomalous Hump Phenomenon in Low-temperature Poly-Si Thin Film Transistors

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density () and grain boundary trap density () extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

Temperature dependence of photocurrent for the AgInS 2 epilayers grown by hot wall epitaxy

A silver indium sulfide () epilayer was grown by the hot wall epitaxy method, which has not been reported in the literature. The grown epilayer has found to be a chalcopyrite structure and evaluated to be high quality crystal. From the photocurrent measurement in the temperature range from 30 K to 300 K, the two peaks of A and B were only observed, whereas the three peaks of A, B, and C were seen in the PC spectrum of 10 K. These peaks are ascribed to the band-to-band transition. The valence band splitting of was investigated by means of the photocurrent measurement. The crystal field splitting, , and the spin orbit splitting, , have been obtained to be 0.150 eV and 0.009 eV at 10 K, respectively. And, the energy band gap at room temperature has been determined to be 1.868 eV. Also, the temperature dependence of the energy band gap, (T), was determined.