Hong-Hui Hsu

Low Programming Current Phase Change Memory Cell with Double GST Thermally Confined Structure

A novel PCM cell with double GST thermally confined structure was proposed and fabricated in this work. by inserting an extra bottom GST layer under the confined GST region, the heat loss can be effectively prevented and the temperature profile over active region becomes more uniform. thus, a low reset current less than 0.3 ma can be achieved and the set performance is also improved to be faster than 200 ns.

Performances of GeSnSbTe Material for High-Speed Phase Change Memory

In this paper, a new application of phase change material GeSnSbTe (GSST) is proposed for high-speed phase-change memory (PCM). The device characteristics of PCM employing GeSnSbTe and conventional Ge2Sb2Te5 (GST) are compared. Because of high crystallization speed, the GSST device demonstrates the benefits of shorter SET pulse, lower SET current, and higher resistance ratio.

The switching behaviors of submicron magnetic tunnel junctions with synthetic antiferromagnetic free layers

The switching behaviors in elliptic shaped (aspect ratio=2) submicron magnetic tunnel junctions using CoFeB single free layer and CoFeB∕Ru∕CoFeB synthetic antiferromagnetic (SAF) free layers are studied. It is found that under considerable stray fields originating from pinned layers, junctions with single free layer show complex switching behaviors with larger Hc variations. In contrast, junctions with SAF free layers exhibit kink-free R‐H loops and less Hc variations. The Hc of junctions with SAF free layers is less dependent on the junction size than that with a single free layer. Furthermore, for junctions smaller than a critical size the SAF free layers have a smaller Hc than single free layers.

Novel T shape structure PCM and Electrical-Thermal Characteristics

Novel interfacial layer structure was proposed with adjustable resistance ratio and more uniform data distribution capabilities. The reduction of writing power can also be expected with further optimizing the materials and corresponding thicknesses. The performance will be even better with the shrinking of contact area

40-100nm contact hole processes of ZEP520A e-beam resist on PCM prototyping applications

ZEP520A e-beam processes for 40-100nm contact holes were studied for application of phase change memory (PCM) device prototyping. Resist baking, e-beam and development process parameters were investigated on the isolated and semi-dense (1:3) contact holes. PAB temperature for minimum exposure dose-to-size (ESIZE) is 70°C. ESIZE of 200°C PAB is 250 μC/cm2 while that of 70°C is 120 μC/cm2 for 100nm contact hole. ESIZE of contact hole increases very quickly as the CD gets smaller than 60nm. CDs with beam currents of 100pA and 200pA are nearly the same while that with 2nA differs much. Sidewall profiles of contact holes exposed by 100pA and 200pA are near 90° while that exposed with 2nA is tapered. ESIZE decreases with development time. Bottom of contact hole is broadened for prolonged development time. CDs after PDB are not changed. There is little difference in CD between isolated and semi-dense patterns. CD uniformity on the corner and center of contact-hole array are around 5% (+/-3σ), showing a very weak proximity effect. Inter-layer mix-and-match processes were applied to PCM manufacturing. Cross-shaped alignment marks results in the strongest signal waveform on TiW bottom electrode than oxide and TiN/Ti. Mix-and-match PCM device structure was, for the first time, ever demonstrated.