Yi-Chan Chen

Low Programming Current Phase Change Memory Cell with Double GST Thermally Confined Structure

A novel PCM cell with double GST thermally confined structure was proposed and fabricated in this work. by inserting an extra bottom GST layer under the confined GST region, the heat loss can be effectively prevented and the temperature profile over active region becomes more uniform. thus, a low reset current less than 0.3 ma can be achieved and the set performance is also improved to be faster than 200 ns.

Steep Slope and Near Non-Hysteresis of FETs With Antiferroelectric-Like HfZrO for Low-Power Electronics

The antiferroelectricity in HfZrO2 (HZO) annealed at 600 °C with an abrupt turn ON of FET characteristics with SSmin = 23 mV/dec and SSavg = 50 mV/dec over 4 decades of IDS is demonstrated. The near non-hysteresis is achieved with an antiferroelectric-like HZO due to a small remanent polarization and a coercive field. A feasible concept of coupling the antiferroelectric and ferroelectric type HZO are used for low-power electronics and the memory applications, respectively.

Challenges and opportunities for HfO X based resistive random access memory

The binary oxide based resistive memories showing superior electrical performances on the resistive switching are reviewed in this paper. The status and challenges of the HfOX based resistive device with excellent memory properties are presented. Several future challenges for the filamentary type switching device are also addressed.

Impact of incomplete set programing on the performance of phase change memory cell

Phase change memory (PCM) cells with T-shaped structure using tungsten heater were fabricated and the cell characteristics concerning the programing pulse width were also investigated in this work. The numerical modeling shows the thermal nonuniformity over the active region due to the considerable thermal sink of tungsten heater results in the amorphous-phase residues and the incomplete set programing. The experimental results reveal the existence of residual amorphous phase and indicate that the incomplete set programing is the dominant factor to degrade the PCM cell performances, such as the sensing margin and the endurance. The strategies to eliminate the incomplete set programing are the optimization in programing pulse width and the replacement of the tungsten heater with higher resistivity metal such as TiAlN.

Enhanced Thermal Efficiency in Phase-Change Memory Cell by Double GST Thermally Confined Structure

A novel phase-change memory cell with a double- confinement structure was proposed and fabricated in this work. By having an additional bottom Ge2Sb2Te5 layer under the electrically confined active region, the heat loss can be effectively prevented. The temperature uniformity over the active region significantly improves and so does the thermal efficiency. Therefore, a low IRESET of about 0.3 mA and a reset power can be achieved. For the SET performance, a pulsewidth as low as 200 ns can be used without compromising the RSET.

Reliability of ambipolar switching poly-Si diodes for cross-point memory applications

Cross-point memory framework provides high capacity, low power consumption, and low cost in nonvolatile-memory (NVM) technology [1,2]. Resistive cross-point memory structure is one of the potential candidates with scaling down beyond the flash memory [3]. In order to increase density for cross-point architecture, the vertical diode is integrated for the controller (Fig. 1) without planar MOSFET or BJT. The metal oxide diode has been reported on the switching devices with high leakage current [4]. The p/n diode has higher ON-current and uni-polar operation for PCM (Phase Change Memory) [5,6], which is compatible with IC process. The characteristic of bipolar programming in RRAM makes the requirement of bi-directional turn-ON behavior for the switching driving device [7]. In this work, the poly-Si n/p/n diode with ambipolar operation for RRAM applications and the stress reliability for programming will be demonstrated.

Magnetic tunneling junction device model for circuit simulation

In this work, we develop the HSPICE macro model of the magnetic tunneling junction (MTJ) devices for circuit simulation. The macro model exhibits the spin behavior of free layer magnetic moment and automatically changes the magnetic resistance when magnetic moment between free and pinned layer changes. The interlayer coupling effect, metal line resistance and bias-dependent MR ratio are also taken into account. An ingenious approximation is used to model the write magnetic field asteroid curve. This macro model can improve the simulation accuracy of MRAM.

Highly robust self-compliant and nonlinear TaO X /HfO X RRAM for 3D vertical structure in 1TnR architecture

Owing to NAND flash technology facing its scaling limit, resistive random access memory (RRAM) with simple film stack and no cross coupling issue between cells is a promising candidate for future high density memory application [1,2]. The 1TnR architecture with 3D vertical RRAM (VRRAM) structure realizes ultra-low bit cost for high compact density array [3,4]. However, this novel 1TnR structure and processes have not been proved yet. To meet requirements of VRRAM array operation, the nonlinear resistive memory with an excellent self-compliance and low current operation is indispensable [5,6]. A large voltage margin for the device operated with compliance current (ΔVCOMP) and high nonlinearity for the device at low resistance state (LRS) with reliable read voltage should be addressed.

Low current and voltage resistive switching memory device using novel Cu/Ta 2 O 5 /W structure

Low current/voltage (∼10 nA/1.0V) resistive switching memory device in a Cu/Ta<inf>2</inf>O<inf>5</inf>/W structure has been proposed. The low resistance state (R<inf>Low</inf>) of the memory device decreases with increasing the programming current from 10 nA to 1mA, which can be useful for multi-level of data storage. This resistive memory devices have stable threshold voltage, good resistance ratio (R<inf>High</inf>/R<inf>Low</inf>) of 5.3×10⁷, good endurance of ≫10³ cycles, and excellent retention (≫11 hours) with resistance ratio of ≫ 9×10³ can be useful in future non-volatile memory applications.

Performances of GeSnSbTe Material for High-Speed Phase Change Memory

In this paper, a new application of phase change material GeSnSbTe (GSST) is proposed for high-speed phase-change memory (PCM). The device characteristics of PCM employing GeSnSbTe and conventional Ge2Sb2Te5 (GST) are compared. Because of high crystallization speed, the GSST device demonstrates the benefits of shorter SET pulse, lower SET current, and higher resistance ratio.