Hong-Kook Min

High-speed and logic-compatible split-gate embedded flash on 28-nm low-power HKMG logic process

We developed a 4Mb split-gate e-flash on 28-nm low-power HKMG logic process, which demonstrates the smallest bit-cell size (0.03×-um2) for high performance IoT applications. High speed operation (25us write time and 2ms erase operation) and robust reliability (500K cycle, 10 years retention) are achieved through optimization of triple-gate flash architecture and scaling of word-line (WL) transistor. New type of high-voltage transistor with LDD-first scheme is applied to enable further scaling of decoder block in Flash IP. Digital-Vdd (1.0V) read operation is used by lowering threshold voltage (Vth) of HV transistor without sacrificing break-down during Flash P/E operation. By using module process concept, the existing RF and logic IP is reused without modification.

Highly Scalable 2nd-Generation 45-nm Split-Gate Embedded Flash with 10-ns Access Time and 1M-Cycling Endurance

We present a highly scalable 2nd generation 45-nm split-gate embedded flash, which has been scaled of 40% unit-cell-size (almost same size with 28-nm technology node) from the 1st generation 45-nm embedded flash without using extra masks, processes and advanced-equipment. By optimizing process of triple-gate flash architecture and implementing several design methodologies, high speed operation (10ns random access time, 25us write time and less than 2ms erase operation) and robust reliability (1M cycle, 20 retention) are achieved. It has been successfully verified in range of 1Mb up to 16Mb density flash IPs.