Duc-Hung Le

Low-Resource Low-Latency Hybrid Adaptive CORDIC With Floating-Point Precision

Despite being proposed since more than 50 years ago, COordinate Rotation DIgital Computer (CORDIC) is still one of the most effective algorithms for elementary function calculation so far. Original CORDIC, however, suffers high latency due to its nature of unvarying number of rotations. As a result, a low-latency hybrid adaptive (HA) CORDIC is proposed in this paper. Firstly, adaptive angle selection decreases total iterations up to 50% with respect to higher accuracy of results. Secondly, hybrid architecture including fixed-point input and floating-point output reduces the total hardware utilization and enhances the dynamic range of final results. Lastly, parallel and pipeline processing together with resource sharing technique allow the design to operate fully at 175.7 MHz with low resource consumption 1,139 LUTs and 489 registers.

A fast CAM-based image matching system on FPGA

A CAM-based (Content Addressable Memory) image matching system is implemented on hardware system using FPGA. The system has simple structure, does not employ any Central Processor Units (CPUs) as well as complicated computations. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the system. Thus increases the matching performance of the system. The system is applied for exact image matching or approximate image matching with various required search patterns without using search principles. In this paper, the authors present the system for fast image matching applications on 2-D data.

Design of a low-power fixed-point 16-bit digital signal processor using 65nm SOTB process

In this paper, a design of 16-bit fixed-point digital signal processor (DSP) is proposed. This DSP is based on the Harvard architecture, having two buses for ALU and a pipeline multiply accumulator (MAC). It composes of 16 general purpose 24-bit registers together with 41 four-cycle instruction sets. The DSP has a simple structure which is compact and flexible. The DSP is designed for low-power consumption, and implemented on ASIC using SOTB 65nm process which is a kind of SOI devices. The DSP chip consumes very low-power consumption 282μW at the operation voltage 0.55V and operation frequency 200MHz.

A fully-parallel information detection hardware system employing Content Addressable Memory

A new information detection method has been proposed for a very fast and efficient search engine. This method is implemented on hardware system using FPGA. We take advantages of Content Addressable Memory (CAM) which has an ability of searching and matching mode for designing the system. The CAM blocks have been designed using available memory blocks of the FPGA device to save access times of the whole system. The entire memory can return multi-matched results concurrently. The system operates based on the CAMs for pattern matching in parallel manner to return multiple addresses of multi-matched results. Based on the parallel multi-matching operations, the system can be applied for pattern matching with various required constraint conditions without using any search principles. The very fast multi-matched results 60ns are achieved at the operational frequency 50 Mhz. Thus increases the matching performance of the information detection system which uses this method as the core system.

A parallel pipeline CORDIC based on adaptive angle selection

Coordinate Rotation Digital Computer (CORDIC) was an efficient algorithm to compute elementary arithmetic such as multiplication, division, and root extractions. However, conventional CORDIC algorithm requires high latency to obtain the results. This paper proposes a low latency parallel pipeline CORDIC (PP-CORDIC) to calculate trigonometric functions. The results show that PP-CORDIC can operate at 83.64 MHz frequency with the latency was 10, 15, and 17 clock cycles in the best, average, and worst case, respectively. The hardware architecture occupies 7,035 LUTs, and 3,409 registers on Stratix IV FPGA.

A CAM-based Information Detection Hardware System for fast exact pattern matching

A CAM-based Information Detection Hardware System for fast exact pattern matching is implemented on a hardware system with FPGA and ASIC. The system has a simple structure, does not employ any Central Processor Unit (CPU) as well as complicated algorithms. We take advantage of Content Addressable Memory (CAM) which has an ability of parallel multi-match mode for designing the system. The system is applied to fast pattern matching with various required search patterns without using any search principles. In this paper, the authors present the system for exact pattern matching on 2-D data.

FPGA-based frequent items counting using matrix of equality comparators

In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the Altera Arria V SoC Development Kit. The experimental results show that the implementation can perform on the maximum clock frequency of 40.85 MHz and requires 51,094 ALUTs and 8,417 registers, which is about 29% of the FPGAs resources. The average throughput performance achieves 1,280 millions items per second, which is about 50 times faster than that of the software-based application at the same setting.

A floating-point FFT Twiddle factor implementation based on adaptive angle recoding CORDIC

In this paper, a single-precision floating-point FFT Twiddle Factor (TF) implementation is proposed. The architecture is based on Adaptive Angle Recoding CORDIC (AARC) algorithm. The TF design is built and verified on Altera Stratix IV FPGA chip and 65nm SOTB synthesis. The FPGA implementation has 103.9 MHz maximum frequency, throughput result of 16.966 Mega-Sample per second (MSps), and resources utilization of 7, 747 ALUTs and 625 registers. On the other hand, the SOTB synthesis has 16, 858 standard cells on an area of 86, 718um2, 166 MHz maximum frequency, and the speed of 27.107 MSps. The accuracy results are 1.133E − 10 Mean-Square-Error (MSE) and about 26 part-per-million (ppm) maximum error-ratio.

A hybrid adaptive CORDIC in 65nm SOTB CMOS process

In this paper, a hybird adaptive Coordinate Rotation Digital Computer (HA-CORDIC) has implemented in 65nm Silicon On Thin Buried oxide (SOTB) CMOS technology. In the HA-CORDIC implementation, the adaptive algorithm is utilized for reducing the iteration of CORDIC algorithm. In comparison with other floating-point CORDIC designs, the latency of our proposed scheme is lower. It spends only 12, 20, and 26 clocks cycles in the best, average, and worst case, respectively. The HA-CORDIC exploits some design techniques such as resource sharing, pipeline, and parallel processing to achieve low-resource and low-latency. In 65nm SOTB CMOS technology, this design is able to operate at 50 MHz frequency with 0.5 V supply voltage, 0.36 mA current, and 0.058 mm2 area. Its power consumption of HA-CORDIC is 0.251 mW, about three times lower than the one in conventional CMOS technology. Its leakage current is about 0.492 μA if the supply voltage VDD is 0.4 V and the bias voltage VBB is -1.5 V. This leakage current is about four times lower than that of HA-CORDIC implementing in conventional CMOS.

High-performance DCT architecture based on angle recoding CORDIC and Scale-Free Factor

In this paper, the authors proposed highperformance DCT architectures based on Coordinate Rotation Digital Computer (CORDIC). The implementations deployed Adaptive angle recoding CORDIC (ACor) method and Scale-Free Factor (SFF) technique. There are two models presented in the paper: ACor-based Chen-DCT (ACor-DCT-C) and ACor-based Loeffler-DCT (ACor-DCT-L). The critical path in both models is six adder-delay. The experimental results give the coding gain performances of 8.8238 dB and 8.8229 dB for ACor-DCT-C and ACor-DCT-L, respectively. The mean-square-error (MSE) results are 6.27e-6 and 4.42e-4 for ACor-DCT-C and ACor-DCT-L, respectively. Each design requires 36 adders and 16 shifters in its implementation.