-Hung Hsieh

A divider-less sub-harmonically injection-locked PLL with self-adjusted injection timing

A low-phase-noise phase-locked loop (PLL) is widely used in clock generation, frequency synthesis, and data conversion. In a PLL using a sub-sampling phase detector (SSPD) achieves not only low phase noise, but also low power. In a low-phase-noise sub-harmonically injection-locked PLL (SIPLL) is presented. The injection timing of a SIPLL is sensitive to the process, voltage, and temperature (PVT) variations. In addition, the divider of a SIPLL [3-5] cannot be powered down to save the power as in [1, 2]. In this paper, a divider-less SIPLL with self-adjusted injection timing is presented.

60GHz high-gain low-noise amplifiers with a common-gate inductive feedback in 65nm CMOS

In this paper, a novel design technique of common-gate inductive feedback is presented for millimeter-wave low-noise amplifiers (LNAs). For this technique, by adopting a gate inductor at the common-gate transistor of the cascode stage, the gain of the LNA can be enhanced even under a wideband operation. Using a 65nm CMOS process, transmission-line-based and spiral-inductor-based LNAs are fabricated for demonstration. With a dc power consumption of 33.6 mW from a 1.2-V supply voltage, the transmission-line-based LNA exhibits a gain of 20.6 dB and a noise figure of 5.4 dB at 60 GHz while the 3dB bandwidth is 14.1 GHz. As for the spiral-inductor-based LNA, consuming a dc power of 28.8 mW from a 1.2-V supply voltage, the circuit shows a gain of 18.0 dB and a noise figure of 4.5 dB at 60 GHz while the 3dB bandwidth is 12.2 GHz.

A V-band self-healing power amplifier with adaptive feedback bias control in 65 nm CMOS

A self-healing two-stage 60 GHz power amplifier (PA) with amplitude/phase compensation is realized in 65 nm CMOS. An adaptive feedback bias scheme with three control knobs is proposed to extend the linear operating region and enhance chip-to-chip performance yield; allowing a 5.5 dB improvement of the output 1-dB compression point (P1dB) and a less than 2% chip-to-chip gain variation. At a 1 V supply, the fully differential PA achieves a saturation output power (Psat) of 14.85 dBm with a peak power-added-efficiency (PAE) of 16.2%. With the on-chip amplitude compensation, the P1dB is extended to 13.7 dBm. With the on-chip phase compensation, the output phase variation is minimized to less than 0.5 degree. To the best of our knowledge, this PA provides the highest Psat and P1dB with simultaneous high PAE for a single PA reported to date. The PA delivers a linear gain of 9.7 dB and has a 7 GHz bandwidth from 55.5 to 62.5 GHz with a very compact area of 0.042 mm2.

A 60GHz on-chip RF-Interconnect with λ/4 coupler for 5Gbps bi-directional communication and multi-drop arbitration

A 5Gbps bi-directional RF-Interconnect (RF-I) with multi-drop and arbitration capabilities is designed and realized in 65nm CMOS. The baseband data are modulated in RF-I by using a 60GHz carrier in ASK format. An on-chip differential transmission line (TL) is used as the communication channel, which minimizes the latency (9ps/mm) only under the speed-of-light limitation. We insert λ/4 directional couplers for implementing multi-drops without signal reflection. We also use MOS switches along the signal path to reconfigure/arbitrate communication priority for multi-drops. This design consists of four TX/RX drops along a 5.5mm TL ring, supports destructive reading with fixed priority, and can reconfigure any drop as the transmitter. The tested data rate of the RF-I is 5Gbps with lower than 10-12 BER. The average power consumptions for the link are 1.33pJ/b and 0.24pJ/b/mm.

An 8Gb/s/pin 4pJ/b/pin Single-T-Line dual (base+RF) band simultaneous bidirectional mobile memory I/O interface with inter-channel interference suppression

The demand for higher power efficiency and bandwidth is increasing as mobile devices keep enhancing its graphic computing and media processing capabilities. Current memory interfaces with single-wire signaling operate at 5Gb/s/pin [1] and 6Gb/s/pin [2] with the power efficiency of 17.4pJ/b/pin and 15.8pJ/b/pin, respectively. Mobile DDR memory I/O with differential signaling has better power efficiency of 6.4pJ/b/pin [3], and so does the prior dual-band interconnect (DBI) [4] with the efficiency of 5pJ/b/pin at 4.2Gb/s/pin for simultaneous bidirectional (SBD) mobile memory I/O interface. However, DBIs differential signaling is incompatible with existing standards, and it also occupies large die area for using differential transmission lines and an LC-oscillator for generating RF-carrier. To alleviate these concerns, we propose to use a Single-Transmission-Line DBI (STL-DBI) with the best figure-of-merit (FoM) defined as data rate per pin divided by the I/O-interface die area and power consumption.

A 100-GHz varactorless CMOS VCO using source degeneration

We present a new varactorless voltage-controlled oscillator (VCO) technique at 100GHz in 65nm CMOS technology. Using source degeneration and capacitors between the source and drain nodes of cross-coupled MOS transistors, the new technique is able to change the output frequency of a VCO in a 100GHz fundamental mode with an at least 4GHz wide tuning range. The phase noise of the VCO is −85.1dBc/Hz at 1MHz offset from the 98.6GHz carrier frequency. The power consumption is 7.4mW when the supply voltage is 1.2V and the maximum output frequency is 102.7GHz.

A V-Band Divide-by-Three Injection-Locked Frequency Divider in 28 nm CMOS

In this letter, the 28 nm CMOS divide-by-three injection-locked frequency divider (ILFD) operating at the V band is presented for the first time. Based on a differential direct injection scheme, the proposed circuit can perform a division ratio of three while an enhanced locking range is achieved due to superior injection efficiency. From the measured results, the core circuit consumes a dc power of 8.8 mW from a 1 V supply voltage. At an incident power level of 0 dBm, the divider exhibits a locking range from 52.61 to 55.12 GHz. Within this frequency range, the output power and phase noise are kept around -5 dBm and -125 dBc/Hz at a 1 MHz offset, respectively.

A 60dB gain and 4dB noise figure CMOS V-band receiver based on two-dimensional passive G m -enhancement

A direct conversion receiver which consists of low noise amplifier (LNA), mixer and programmable gain amplifier (PGA) for V-band (60GHz) applications is designed and realized in 65nm CMOS. A novel two-dimensional passive gm-enhancement technique is devised to boost the conversion gain and lower the Noise Figure (NF) with insignificant power overhead. An overall minimum SSB NF of 3.9dB and a maximum power conversion gain of 60dB have been validated from such fabricated receiver that occupies core silicon area of 0.2mm2 and draws 34mA from 1V supply.

D-band frequency synthesis using a U-band PLL and frequency tripler in 65nm CMOS technology

This paper presents a digitally controlled frequency synthesizer in 65nm CMOS technology for D-band transceiver applications. The synthesizer uses a low frequency U Band (44–48 GHz) phase-locked loop to track a 50 MHz reference and then employs an injection locked frequency tripler (ILFT) to provide output that can be tuned between 130 and 133 GHz. The proposed D-band synthesizer offers a directly measured phase noise of −82.5 dBc/Hz at 1 MHz offset from the carrier and consumes 92mW of power. The entire syntheszier occupies 0.68mm2 of silicon area.

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

Power and bandwidth requirements have become more stringent for DRAMs in recent years. This is largely because mobile devices (such as smart phones) are more intensively relying on the use of graphics. Current DDR memory I/Os operate at 5Gb/s with a power efficiency of 17.4mW/Gb/s (i.e., 17.4pJ/b)[1], and graphic DRAM I/Os operate at 7Gb/s/pin [3] with a power efficiency worse than that of DDR. High-speed serial links [5], with a better power efficiency of ∼1mW/Gb/s, would be favored for mobile memory I/O interface. However, serial links typically require long initialization time (∼1000 clock cycles), and do not meet mobile DRAM I/O requirements for fast switching between active, standby, self-refresh and power-down operation modes [4]. Also, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly [4] for extended bandwidth due to the need of power hungry pre-emphasis, and equalization circuits.