Tzu-Jin Yeh

High-performance integrated fan-out wafer level packaging (InFO-WLP): Technology and system integration

Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLPs high Q inductors can enhance electrical performance and lower power consumption in RF circuit applications.

High-Performance Slow-Wave Transmission Lines With Optimized Slot-Type Floating Shields

A novel slow-wave transmission line with optimized slot-type floating shields in advanced CMOS technology is presented. Periodical slot-type floating shields are inserted beneath the transmission line to provide substrate shielding and to shorten the electromagnetic (EM) propagation wavelength. This is the first study that demonstrates how the wavelength, attenuation loss, and characteristic impedance can be adjusted by changing the strip length (SL), strip spacing (SS), and metal layer position of the slot-type floating shields. Wavelength shortening needs to be achieved with a tradeoff between slow-wave effect and attenuation loss. The slot-type floating shields with different SLs, SSs and metal layer positions are analyzed. It is concluded that minimum SL provides the most optimal result. A design guideline can be established to enable circuit designers to reach the most appropriate slot-type floating shields for optimal circuit performance. Transmission line test structures were fabricated by using 45-nm CMOS process technology. Both measurement and EM waves simulation were performed up to 50 GHz. Transmission lines are frequently used at a length of half- or quarter-wavelength. With a shortened wavelength, a saving in silicon area of more than 67% can be achieved by using optimized slot-type floating shields. Experimental results demonstrated a higher effective relative permittivity value, which is improved by a factor of more than 9, and a better quality factor, which is improved by a factor of more than 6, as compared to conventional transmission lines.

Broadband small-signal model and parameter extraction for deep sub-micron MOSFETs valid up to 110 GHz

A broadband small-signal model suitable for deep sub-micron MOSFET high frequency applications and its parameter extraction have been proposed and demonstrated. Using a 110 GHz millimeter wave S-Parameter measurement, we directly extracted the parameters and fitted very well within a broad range from 45 MHz up to 110 GHz. This is a state-of-the-art technique that demonstrates the model up to 110 GHz and can be considered as an initial method for an optimization procedure to be used for more complete models.

Design of 60-GHz Low-Noise Amplifiers With Low NF and Robust ESD Protection in 65-nm CMOS

This paper presents two 60-GHz low-noise amplifiers (LNAs) with different electrostatic (ESD) protection schemes, including the diode-based and LC-based configurations. By codesigning ESD network and input matching, both LNAs are optimized for minimum noise figure (NF) while maintaining a similar gain. Compared with the conventional double-diode approach, the proposed LC-based design uses a high current capability spiral inductor and a high breakdown voltage metal-oxide-metal capacitor as effective bidirectional ESD protection, showing much improved ESD protection level and NF under reduced power consumption. The test results demonstrate an over 8-kV human-body-model ESD level and an over 13-A very fast transmission line pulse current level for charge-device-model ESD protection. The measured NF and power gain are 5.3 dB and 17.5 dB, respectively, at 58 GHz, under a power consumption of only 18 mW. To the best of our knowledge, the LC-based ESD-protected LNA demonstrates a highest ESD protection level with a lowest NF, compared with prior arts operating at similar frequencies.

On the millimeter-wave characteristics and model of on-chip interconnect transmission lines up to 110 GHz

On-chip microstrip and coplanar waveguide structures were designed and fabricated in RF CMOS foundry processes. The wideband transmission line characteristics such as characteristic impedance, attenuation constant, propagation delay, and their electrical RLC parameters were evaluated based on S-parameter measurements in the millimeter-wave range. In addition, a SPICE-compatible RLC lumped element model including the skin-effect and the substrate RC network is employed to account for transmission line effects in interconnect over a wide frequency range up to 110 GHz.

A 17.5–26 GHz Low-Noise Amplifier With Over 8 kV ESD Protection in 65 nm CMOS

By the electrostatic discharge (ESD)/matching co-design methodology, a wideband low-noise amplifier (LNA) using a grounded spiral inductor in conjunction with a MOM capacitor for ESD protection and wideband matching is demonstrated in a 65 nm CMOS. The shunt inductor provides an effective bidirectional ESD protection to the ground and the series capacitor greatly enhances the breakdown level in the current discharge path. The measurement results demonstrate an over 8 kV human-body-model ESD protection level with almost no RF characteristic degradation after ESD zapping. Under a power consumption of 5.6 mW, the ESD-protected LNA presents a flat NF and power gain of 3.3-3.9 dB and 16.6-17.9 dB, respectively, in the frequency range of 18.5-24.5 GHz, and a 3 dB bandwidth of 17.5-26 GHz is achieved.

Characterization and model of on-chip flicker noise with deep Nwell (DNW) isolation for 130nm and beyond SOC

An investigation of the flicker noise, by exploring 0.13 /spl mu/m and beyond MS/RF CMOS technology, was carried out for wireless system-on-a-chip (SOC) applications. The on-chip flicker noise of various components are characterized and accurately modeled. The feasibility of deep N-well isolation to suppress substrate coupling of analog nodes from digital clock noise is also demonstrated.

BSIM4 high-frequency model verification for 0.13 /spl mu/m RF-CMOS technology

A compact model capable of simulating both DC and RF characteristics is highly desirable. This work is the first report of an extensive experimental evaluation of the accuracy of the BSIM4 model at high frequencies using a 0.13 /spl mu/m RF-CMOS process. The accuracy of the model is verified on both N-channel and P-channel devices through small-signal S-parameter measurements up to 50 GHz, 1/f noise measurements, and noise figure measurements in the 2-GHz to 6-GHz range.

An investigation of the RF/analog characteristics of multiple variants SiGe HBTs for optical and wireless applications

Multiple variants of SiGe HBTs, using selected collector implants, suitable for wired and wireless applications were explored. The RF/analog characteristics of HBTs featured with fT/BV/sub CEO/ values of 130 GHz/2.3 V, 80 GHz/3.4 V and 60 GHz/ 4.8 V were characterized. The dependence of bias, temperature, frequency, noise, power, and geometry were investigated to provide designers with appropriate performance-breakdown design coverage and flexibility.

Characterization and model of high quality factor and broadband integrated inductor on Si-substrate

Proton bombardment has been used to boost the on-chip inductor quality factor and to also improve the frequency response. In this paper we demonstrated these advantages using the 0.13/spl mu/m and 0.18/spl mu/m RF CMOS processes. Based on the model, we evaluated how the performance improved using bombardment technology. A simultaneously impressive increase both in the peak Q-value and the optimal frequency have been evidenced due to its significantly reduced substrate parasitic effect as a result of higher substrate resistivity. This can be considered as a solution to integrate inductor on a Si substrate.