Hsinyu Tsai

Sub-30 nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly

The authors demonstrate pattern transfer of 29-nm-pitch self-assembled line-space polystyrene-poly(methyl methacrylate) patterns generated by graphoepitaxy into three important materials for semiconductor device integration: silicon, silicon nitride, and silicon oxide. High fidelity plasma etch transfer with production-style reactors was achieved through co-optimization of multilayer masking film stacks and reactor conditions. The authors present a systematic study of the line edge roughness (LER) and line width roughness evolution during pattern transfer. Application of a postetch annealing process shows reduction of the LER of silicon features from around ∼3 nm to less than 1.5 nm. These results further demonstrate that directed self-assembly-based patterning may be a suitable technique for semiconductor device manufacturing.

Computational Aspects of Optical Lithography Extension by Directed Self-Assembly

EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.

Directed self-assembly process implementation in a 300mm pilot line environment

The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy guiding pattern was created by the IBM Almaden approach using brush materials in combination with an optional chemical slimming of the resist lines. Critical dimension (CD) uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of the DSA process were characterized. CD rectification and LWR reduction were observed. The chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly improving the DSA PW under over-dose conditions. However, the overall PW was found to be smaller than without using the slimming, due to a new failure mode at under-dose region.

Pattern transfer of directed self-assembly patterns for CMOS device applications

Abstract. A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

Computational lithography platform for 193i-guided directed self-assembly

We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more predictive than compact model but much faster then the physics-based MC model. However simplifying the model might lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm based lithography process using DSA.

Design technology co-optimization assessment for directed self-assembly-based lithography: design for directed self-assembly or directed self-assembly for design?

Abstract. We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.

Resistivity of copper interconnects beyond the 7 nm node

The resistivity of damascene copper is measured at pitch ranging down to 40 nm and copper cross-sectional area as low as 140 nm2. Metallization by copper reflow is demonstrated at 28 nm pitch with patterning by directed self-assembly (DSA). Extremely low line-edge-roughness (LER) is attained by surface reconstruction of a single crystal silicon mask. Variation of LER is found to have no impact on resistivity. A resistivity benefit is found for wires with nearly bamboo grain structure, offering the promise of improved performance beyond the 7 nm node if grain size can be controlled.

Customization and design of directed self-assembly using hybrid prepatterns

Diminishing error tolerance renders the customization of patterns created through directed self-assembly (DSA) extremely challenging at tighter pitch. A self-aligned customization scheme can be achieved using a hybrid prepattern comprising both organic and inorganic regions that serves as a guiding prepattern to direct the self-assembly of the block copolymers as well as a cut mask pattern for the DSA arrays aligned to it. In this paper, chemoepitaxy-based self-aligned customization is demonstrated using two types of organic-inorganic prepatterns. CHEETAH prepattern for “CHemoepitaxy Etch Trim using a self-Aligned Hardmask” of preferential hydrogen silsesquioxane (HSQ, inorganic resist), non-preferential organic underlayer is fabricated using electron beam lithography. Customized trench or hole arrays can be achieved through co-transfer of DSA-formed arrays and CHEETAH prepattern. Herein, we also introduce a tone-reversed version called reverse-CHEETAH (or rCHEETAH) in which customized line segments can be achieved through co-transfer of DSA-formed arrays formed on a prepattern wherein the inorganic HSQ regions are nonpreferential and the organic regions are PMMA preferential. Examples of two-dimensional self-aligned customization including 25nm pitch fin structures and an 8-bar “IBM” illustrate the versatility of this customization scheme using rCHEETAH.

Pattern transfer of directed self-assembly (DSA) patterns for CMOS device applications

We present a study on the optimization of etch transfer processes for circuit relevant patterning in the sub 30 nm pitch regime using directed self assembly (DSA) line-space patterning. This work is focused on issues that impact the patterning of thin silicon fins and gate stack materials. Plasma power, chuck temperature and end point strategy is discussed in terms of their effect on critical dimension (CD) control and pattern fidelity. A systematic study of post-plasma etch annealing processes shows that both CD and line edge roughness (LER) in crystalline Si features can be further reduced while maintaining a suitable geometry for scaled FinFET devices. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode and a SiN capping layer are also presented. We conclude with the presentation of a strategy for realizing circuit patterns from groups of DSA patterned fins. These combined results further establish the viability of DSA pattern generation as a potential method for CMOS integrated circuit patterning beyond the 10 nm node.