Yong-Tian Hou

Spatial and energetic distribution of border traps in the dual-layer HfO2∕SiO2 high-k gate stack by low-frequency capacitance-voltage measurement

Threshold voltage instability measured by the pulse current-voltage technique has been recognized as the transient charging and discharging of the preexisting bulk traps in Hf-based high-k gate dielectrics, and these high-k traps or called border traps can instantly exchange charge carriers with the underlying Si substrate by tunneling through the thin interfacial oxide. Based on an elastic tunneling model through trapezoidal potential barriers, the spatial and energetic distribution of border traps in the HfO2∕SiO2 high-k gate stack can be profiled as a smoothed, three-dimensional mesh by measuring the low-frequency capacitance-voltage characteristics of high-k metal-oxide-semiconductor capacitors with n-type Si substrate.

Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high-k/SiO2 gate stacks

The strain effect and channel length dependence of bias temperature instability on dual metal gate complementary metal-oxide-semiconductor field enhanced transistors with HfSiON dielectric were studied in detail. For channel length larger than 0.1 μm, both positive and negative bias temperature instabilities (PBTI and NBTI) were not affected by the tensile strain obviously. As the channel scaling down to less than 0.1 μm, the degradation after PBTI stress was still not influenced by the strain, however, the NBTI degradation was enhanced significantly. In addition, the dependence of BTI on channel length was extensively investigated under constant voltage and field stress.

High-Temperature Stable HfLaON p-MOSFETs With High-Work-Function

We report a novel 1000 degC stable HfLaON p-MOSFET with Ir3 Si gate. Low leakage current of 1.8times10-5 A/cm2 at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm2/Vmiddots are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degC rapid thermal annealing is fully compatible to current very large scale integration fabrication lines

\hbox{Ir}_{3}\hbox{Si}

A comprehensive study on bulk trap enhanced gate-induced drain leakage (BTE-GIDL) currents in high-MOSFETs is reported in this letter. The dependence of GIDL for various parameters, including the effect of Zr concentration in , high-film thickness, and electrical stress is investigated. The incorporation of Zr into reduces GIDL. GIDL was also found to reduce with thinner high-film. In addition, a significant correlation between GIDL and bulk trap density in high- film is established. Possible mechanisms were provided to explain the role of bulk trapping in BTE-GIDL, observed in high-devices.

Gate

A novel 1000 degC-stable IrxSi gate on HfSiON is shown for the first time with full process compatibility to current very-large-scale-integration fabrication lines and proper effective work function of 4.95 eV at 1.6-nm equivalent-oxide thickness. In addition, small threshold voltages and good hole mobilities are measured in IrxSi/HfSiON transistors. The 1000 degC thermal stability above pure metal (900 degC only) is due to the inserted 5-nm amorphous Si, which also gives less Fermi-level pinning by the accumulated metallic full silicidation at the interface

Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs

This paper reports a comprehensive study on the influence of nitrogen incorporation on high-k (HK) device performance and reliability. Two approaches including dielectric nitrogen annealing and interfacial layer (IL) nitrogen annealing are investigated. It is found the HK nitrogen annealing is a better solution for the trade-off between mobility and inversion oxide thickness than IL annealing. The positive bias temperature instability characteristic is improved by HK annealing. However, the HK nitrogen annealing lowers the barrier of dielectric and thus results in an abnormally high leakage current.

High-Temperature Stable

This paper reports the BTI reliability of dual metal gate CMOSFETs with Hf-based dielectrics including HfO2 and HfSiON. Severer PBTI degradation was observed on HfO2 NMOSFETs and two NBTI degradation behaviors were observed on HfO2 pMOSFET. The strain effect and channel length dependence on BTI were also investigated. Mechanical strain degrades NBTI but has no effect on PBTI. As channel length scaling down, both PBTI and NBTI are mitigated.

\hbox{Ir}_{x}\hbox{Si}

This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.