Liang-Gi Yao

Process-strained Si (PSS) CMOS technology featuring 3D strain engineering

We report the demonstration of a process-strained Si (PSS) CMOS technology using the concept of three-dimensional (3D) strain engineering. Methods of producing PSS include stress engineering of trench isolation, silicide, and cap layer, to improve NMOS and PMOS performance simultaneously. Each of these approaches results in a 5-10% enhancement in the ring oscillator (RO) speed. By taking advantage of preferential 3D strain engineering via one or combining more PSS techniques, CMOS performance can be further improved. PSS is a cost effective technology for meeting CMOS power-performance requirements.

Effect of polycrystalline-silicon gate types on the opposite flatband voltage shift in n-type and p-type metal-oxide-semiconductor field-effect transistors for high-k-HfO2 dielectric

Hafnium dioxide (HfO2) gate dielectrics formed by the atomic layer deposition (ALD) process were fabricated to investigate the flatband voltage shift (ΔVFB) relative to SiO2. It is found that the direction of ΔVFB depends on the Fermi level position in the gate material, which shows respective positive and negative shifts in n-type and p-type metal–oxide–semiconductor field-effect transistors (MOSFETs), regardless of the substrate type. The opposite direction in the flatband voltage shift is attributed to both acceptor- and donor-like interface states existing at the interface between the polycrystalline-silicon (poly-Si) gate and HfO2 dielectric. A model is proposed to explain the effects of poly-Si gate type on the flatband voltage shift in MOSFETs.

High performance tantalum carbide metal gate stacks for nMOSFET application

A systematic study is performed on tantalum carbide (TaC) metal electrode on HfO2 and HfSiON dielectrics using conventional CMOS process. TaCs effective work function (EWF) is estimated to be 4.28 eV on HfO2 using Vfb~EOT methodology, where both interfacial oxide and high-K film thickness are varied and thus charge effect is corrected successfully. Investigation of the EWF dependence on underlying dielectrics reveals that TaC EWF on HfSiON is about 0.17eV higher than that on HfO2. This phenomenon cannot be explained by the usual metal induced gap states (MIGS) theory. In addition, mobility higher than 90% of poly/SiO2 reference and EOT scaling down to 12.5A has been achieved. Reduction of HfO2 thickness is identified as an effective approach to suppress charge trapping in the gate stack. With reduced thickness, threshold voltage stability and electron mobility are significantly improved. All these results prove that TaC/high-K stack is a promising candidate in nMOSFET application

A low operating power FinFET transistor module featuring scaled gate stack and strain engineering for 32/28nm SoC technology

We show that FinFET, a leading transistor architecture candidate of choice for high performance CPU applications [1–3], can also be extended for general purpose SoC applications by proper device optimization. We demonstrate superior, best-in-its-class performance to our knowledge, as well as multi-Vt flexibility for low-operating power (LOP) applications. By high-k/metal-gate (HK/MG) and process flow optimizations, significant drive current (ION) improvement and leakage current (IOFF) reduction have been achieved through equivalent oxide thickness (EOT) scaling and carrier mobility improvement. N-FinFET and P-FinFET achieve, when normalized to Weff (Weff=2xHf+Wf), ION of 1325 µA/µm and 1000 µA/µm at 1 nA/µm leakage current under VDD of 1 V, and 960 uA/um and 690 uA/um at 1 nA/um under Vdd of 0.8V, respectively. This FinFET transistor module is promising for a 32/28nm SoC technology.

Substrate-strained silicon technology: process integration [CMOS technology]

We demonstrate a 60 nm gate length substrate-strained Si CMOS technology and the fastest reported ring oscillator speed of 6.5 ps at 1.2 V operation. The largest enhancement (15%) in I/sub on/-I/sub off/ characteristics without correction for self-heating effects is also reported. The substrate-strained Si process is optimized to enhance manufacturability and circumvent difficulties associated with the integration of the strained Si/SiGe heterostructure. We also report a phenomenon responsible for increased the off state leakage in strained Si devices and a way to suppress it. Surmounting key integration challenges faced by the Si/SiGe heterostructure is critical for its introduction as a manufacturable process.

The 1.3–1.6 nm nitrided oxide prepared by NH3 nitridation and rapid thermal annealing for 0.1 μm and beyond CMOS technology application

Abstract High quality and high performance gate dielectrics prepared by NH 3 nitridation, with equivalent oxide thickness (EOT) down to 1.3–1.6 nm, were firstly investigated. NH 3 nitridation can effectively reduces the EOT to a lower down gate leakage current for more than one order in comparison to the control oxide with identical EOT. More significant barrier height lowering in valence band than in conduction band leads to inferior gate leakage behavior in PMOS after NH 3 nitridation. In addition, NH 3 nitrided NMOS shows a significant improvement in current drivability. But, larger V fb shift and drivability degradation were observed in PMOS. Fortunately, the most of them can be reduced with post-deposition annealing to meet the process target. The quality and reliability were also exanimated by the hysteresis, temperature and time-to-breakdown characteristics.

Modeling of the gate leakage current reduction in MOSFET with ultra-thin nitrided gate oxide

Abstract The origins of different gate leakage behaviors for both PMOS and NMOS with ultra-thin nitrided gate oxide have been studied and modeled. Both equivalent oxide thickness (EOT) and barrier lowering are affected the gate leakage. In NMOS with nitrided oxide, the advantage of EOT decrease is larger to offset the barrier lowering, thus improvement on gate current reduction rate ( R J g ). The situation in PMOS is just contrary to the NMOS, therefore the gate leakage increased with increasing nitridation time. We attribute this to the different barrier lowering in conduction band and valence band.

Effects of Base Oxide Thickness and Silicon Composition on Charge Trapping in HfSiO/SiO2 High-k Gate Stacks

This work investigates the fundamentals of charge trapping and the effects of base oxide thickness and Si composition on charge trapping in HfSiO/SiO2 high-k gate stacks using positive-bias temperature (PBT) stressing scheme. During the PBT stress, threshold voltage shift and saturation drain current degradation induced by charge trapping continue to grow and eventually become saturated, whereas the subthreshold swing and maximum transconductance remain unchanged. The extent of charge trapping increases with the decrease of base oxide thickness and Si composition in the HfSiO film, which can be explained by considering the channel-to-bulk tunneling time constant and the amount of neutral Hf–OH trapping centers in the HfSiO bulk layer. The power law dependence of saturation drain current degradation on the gate bias voltage indicates that charge trapping would become more significant if thin base oxide and low Si composition were employed in the further scaled HfSiO/SiO2 high-k gate stacks.

Novel Strained-Si Substrate Technology for Transistor Performance Enhancement

Strained-Si channel transistors offer significant perforrnance enhancement. However, most designs based on bulk-Si subsfrates utilize thick SiGe buffer layers or complex multi-layer structures for the intoduction of tensile strain in the Si channel and might not be easily or economically integrated into a conventional cMos process t1]. Various methods to irnplement sfiained-Si subsfrates based on silicon-on-insulator (SOf wafers have also been demonstated [2]-[3], but they suffer from an inherent high cost and process corrplexity. In this paper, we present a new, inexpensive, and manufactuable strained-Si substrate technology based on bulk-Si subsfiate, and demonstrate significant enhancement in fransistor perfonnance.