Woei Cherng Wu

Suppression of interfacial reaction for HfO2 on silicon by pre-CF4 plasma treatment

In this letter, the effects of pre-CF4 plasma treatment on Si for sputtered HfO2 gate dielectrics are investigated. The significant fluorine was incorporated at the HfO2∕Si substrate interface for a sample with the CF4 plasma pretreatment. The Hf silicide was suppressed and Hf–F bonding was observed for the CF4 plasma pretreated sample. Compared with the as-deposited sample, the effective oxide thickness was much reduced for the pre-CF4 plasma treated sample due to the elimination of the interfacial layer between HfO2 and Si substrate. These improved characteristics of the HfO2 gate dielectrics can be explained in terms of the fluorine atoms blocking oxygen diffusion through the HfO2 film into the Si substrate.

Characterization of CF4-plasma fluorinated HfO2 gate dielectrics with TaN metal gate

In this paper, fluorine incorporation into the HfO2 gate dielectrics by post CF4 plasma treatment was proposed to improve the electrical characterization. TaN–HfO2–p-Si capacitors were demonstrated in this work. The characteristics of fluorinated HfO2 gate dielectrics were improved, including the capacitance-voltage hysteresis and current-voltage behaviors. This may be attributed to the fluorine incorporated into the HfO2 gate dielectrics as revealed by secondary ion mass spectroscopy. Moreover, the formation of Hf-F bonding was observed through electron spectroscopy for chemical analysis spectra.

High-Performance HfO2 Gate Dielectrics Fluorinated by Postdeposition CF4 Plasma Treatment

Downlo High-Performance HfO2 Gate Dielectrics Fluorinated by Postdeposition CF4 Plasma Treatment Woei Cherng Wu, Chao Sung Lai, Jer Chyi Wang, Jian Hao Chen, Ming Wen Ma, and Tien Sheng Chao Department of Electrophysics and Department of Electronic Engineering, National Chiao Tung University, Hsinchu, Taiwan Department of Electronic Engineering, Chang Gung University, Kwei-Shan, Tao-Yuan, Taiwan Nanya Technology Corporation, Kueishan, Taoyuan, Taiwan

Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High-

In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with gate dielectric are well investigated for the first time. Under room temperature stress condition, the. PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for LTPS-TFT. In addition, an abnormal behavior of the degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of devices performance under high-temperature stress condition can be attributed to the damages of both the gate dielectric and the poly-Si grain boundaries.

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In this work, we describe the characteristics of silicon surface fluorine implantation (SSFI) for HfO2 films with high-temperature postdeposition annealing. The thermal stability of HfO2 gate dielectrics is much improved owing to the incorporation of fluorine into HfO2 thin films. The gate leakage current of the SSFI HfO2 films is about three orders less than that of samples without any fluorine implantation. In addition, improvements in stress-induced leakage current (SILC) and charge trapping characteristics are realized in the HfO2 films with the SSFI. The incorporation of fluorine atoms into the HfO2 films reduces not only interface dangling bonds but also bulk traps, which is responsible for the improvements in properties.

Gate Dielectric

In this article, the current transport mechanism of fluorinated HfO 2 gate dielectrics is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the energy band diagrams and current transport mechanisms for TaN/HfOF/fluorinated-interfacial layer (IL)/Si structures. In particular, we have obtained the following quantities that will be useful for modeling and simulation: (i) fluorinated IL/Si barrier height (or conduction band offset): 3.2 eV; (ii) TaN/HfOF barrier height: 2.6 eV; and (iii) trap levels at 1.3 eV (under both gate and substrate injections) below the HfOF conduction band which contributes to Frenkel-Poole conduction.

Characteristics of Fluorine Implantation for HfO2 Gate Dielectrics with High-Temperature Postdeposition Annealing

In this paper, the current transportation mechanism of HfO2 gate dielectrics with a TaN metal gate and silicon surface fluorine implantation is investigated. Based on the experimental results of the temperature dependence of gate leakage current and Fowler-Nordheim tunneling characteristics at 77 K, we have extracted the current transport mechanisms and energy band diagrams for TaN/HfO2/IL/Si structures with fluorine incorporation, respectively. In particular, we have obtained the following physical quantities: 1) fluorinated and as-deposited interfacial layer (IL)/Si barrier heights (or conduction band offsets) at 3.2 and 2.7 eV; 2) TaN/fluorinated and as-deposited HfO2 barrier heights at 2.6 and 1.9 eV; and 3) effective trapping levels at 1.25 eV (under both gate and substrate injections) below the HfOF conduction band and at 1.04 eV (under gate injection) and 1.11 eV (under substrate injection) below the HfO2 conduction band, which contributes to Frenkel-Poole conduction.

Current Transport Mechanism for HfO2 Gate Dielectrics with Fluorine Incorporation

In this study, a novel approach was proposed to improve the characterization of HfO2. Fluorine was incorporated by CF4 plasma to improve the HfO2 gate dielectric properties including leakage current, breakdown voltage and hysteresis. The hysteresis of capacitance–voltage characteristics can be reduced to approximately 10% hysteresis voltage for the samples with CF4 plasma treatment. An inner-interface trapping model is presented to explain the hysteresis. The secondary-ion mass spectroscopy (SIMS) results show that there is a significant incorporation of fluorine (F) at the interface between the HfO2 thin film and silicon substrate. The incorporation of F effectively suppressed leakage current and improved carrier trapping without an increase in interfacial layer thickness.

Carrier Transportation Mechanism of the Structure With Silicon Surface Fluorine Implantation

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage VTH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility muFE ~ 240 cm2/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 nm.

Effects of Post CF4 Plasma Treatment on the HfO2 Thin Film

The characteristics of CoTiO3 high-k dielectric prepared by sol-gel spin coating method had been demonstrated. High electrical permittivity (k∼40.2) of CoTiO3 dielectric was extracted via the transmission electron microscopy image and capacitance-voltage curves. In addition, the valence band offset between thermal SiO2 and spin-on CoTiO3 was about 4.0 eV, which was detected by x-ray photoelectron spectroscopy. The band gaps of thermal SiO2 and spin-on CoTiO3 were 9.0 and 2.2 eV, respectively. Energy band alignment of spin-on CoTiO3 directly with SiO2 and indirectly with Si was determined in this work.