Hye-jin Kim

A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput

A 512Mb diode-switch PRAM is developed in a 90nm CMOS technology. A core configuration, read/write circuit techniques, and a charge-pump system for the diode-switch PRAM are described. Through these schemes, the PRAM achieves read throughput of 266MB/S and maximum write throughput of 4.64MB/S with a 1.8V supply.

A 0.1-

A 256-Mb phase-change random access memory has been developed, featuring 66-MHz synchronous burst-read operation. Using a charge pump system, write performance was characterized at a low supply voltage of 1.8 V. Measured initial read access time and burst-read access time are 62 and 10 ns, respectively. The write throughput was 0.5 MB/s with internal times2 write and can be increased to ~2.67 MB/s with times16 write. Endurance and retention characteristics are measured to be 107 cycles and ten years at 99 degC

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A 1.8 V 64 Mb phase-change RAM with improved write performance is fabricated in a 0.12 /spl mu/m CMOS technology. The improvement of RESET and SET distributions is based on cell current regulation and multiple step-down pulse generators. The read access time and SET-write time are 68 ns and 180 ns respectively.

1.8-V 256-Mb Phase-Change Random Access Memory (PRAM) With 66-MHz Synchronous Burst-Read Operation

High-K (HK) & Metal-Gate (MG) transistor technology have become a mainstream for the logic & SOC processes. On HK/MG process, bias-temp instability (BTI) poses continuous challenges on the technology scaling despite the reduced Vcc. In recent technologies, PMOS NBTI degradation is increased while NMOS PBTI was reduced with HK scaling. Interfacial Layer (IL) scaling underneath the HK that affects PMOS NBTI and device performance is very challenging. Impact of technology scaling on BTI and BTI on FinFET technology is discussed.

Enhanced write performance of a 64 Mb phase-change random access memory

A 256Mb PRAM featuring synchronous burst read operation is developed. Using a charge-pump system, write performance is characterized at 1.8V supply. Measured initial read access time and burst-read access time are 62ns and 10ns, respectively. The maximum write throughput is 3.3MB/S

Technology scaling on High-K & Metal-Gate FinFET BTI reliability

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

A 0.1/spl mu/m 1.8V 256Mb 66MHz Synchronous Burst PRAM

P+ to p+ isolation degradation that causes DRAM standby current failure under burn-in mode operation is investigated. Although the isolation of the test devices dose not show any degradation or weakness in conventional electrical characterization, it is found that the degradation can be observed by a carrier injection method. Using the simple carrier injection method to simulate the real operating condition of a DRAM chip, a potential problem of the isolation degradation can be easily found, which cannot be screened by conventional electrical measurement.

Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

This paper proposes an improved modulated carrier control with on-time doubler for the single-phase shunt active power filter, which eliminates harmonic and reactive currents drawn by nonlinear loads. This control method directly shapes the line current to be sinusoidal and in phase with the grid voltage by generating a modulated carrier signal with a resettable integrator, comparing the carrier signal to the average line current and making duty ratio doubled. Since the line current compared to the carrier signal is not the peak, but the average value, dc-offset appeared at the conventional control methods based on one-cycle control is effectively addressed. The proposed control technique extirpates the harmonic and reactive currents and solves the dc-offset problem. The operation principle and stability characteristic of the single-phase shunt active power filter with the proposed control method are discussed, and experimental results with laboratory prototype under various load conditions verify its performance.

Evaluation of STI degradation causing DRAM standby current failure in burn-in mode operation using a carrier injection method

In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

Improved Modulated Carrier Control With On-Time Doubler for a Single-Phase Shunt Active Power Filter

Display Driver IC is used to operate the display panel of mobile devices, such as handheld smartphones and tablets. Low power consumption becomes very important in mobile segments, thus High-k (HK)/ metal-gate (MG) process was used to fabricate DDI products. In this paper, an abnormal leakage increase observed during HTOL will be discussed along with the physical mechanism and superb HTOL results after process fixes have been implemented. As result, final DDI product showed an excellent reliability results through 1500hrs of HTOL exceeding product end of life (EOL).