Hyeonseok Hwang

Optimization of resonant inductive links for wireless power transfer

A shunt-series mixed resonant coupled structure for the wireless power transfer (WPT) applications is proposed. If the coils are designed to have proper inductance values, the power transfer efficiency depending on distance has proportional relation only to the shunt capacitors. It enables that the proposed structure facilitates tracking the maximum WPT efficiency according to distance. In the experiment, two pairs of resonant square coils on PCB with different turn ratio (5/10 turn) are compared for 6.78 MHz operation. Both coils have almost same maximum WPT efficiency by optimizing the series and shunt capacitors. But the 10-turn coil only demonstrates aforementioned relation. The proposed structure with 10-turn coil shows that the efficiency of 77.7 % is achieved at a distance of 30 mm.

Investigation of wireless power transfer in multi-coil environment

In this study, simulations and experiments on wireless power transfer (WPT) in a multi-coil environment are conducted under the conditions of multiple battery charging. A series-arrayed 4-coil system comprising one WPT system and three identical WPT systems placed in parallel are investigated in this work. We show that low-frequency wireless power transfer is affected by multiple coils placed in parallel within a confined area. The power transfer efficiency at low frequencies can be degraded by 20% as compared to that of a single WPT system.

A 13.56 MHz CMOS ring oscillator for wireless power transfer receiver system

A 13.56 MHz CMOS ring oscillator for DC/DC converter is demonstrated where measured performances make it suitable for wireless power transfer receiver system. The proposed structure employs a supply-regulated ring oscillator with a temperature compensated current bias circuit, which minimizes the frequency sensitivity to supply and temperature variations. Fabricated in a 0.11 μm 1P5M CMOS process, the developed oscillator as a switching frequency generator of DC/DC converter dissipates maximum 6.8 mW while exhibiting ±0.88 % frequency error against temperature variation of 0-125 °C.

A 6MHz CMOS reference clock generator with temperature and supply voltage compensation

A 6MHz CMOS reference clock generator is presented in 0.18um CMOS process. The proposed structure adopts a current starved type ring oscillator with low drop out (LDO), and temperature compensated current bias. This structure minimized the effects of supply and temperature to frequency error. The reference clock generator achieves frequency variation of less than ±0.26% against supply variation of 3V ~ 5V and ±0.22% against temperature variation of -20°C ~ 100°C.

A wideband cmos cascaded variable gain amplifier using unequally distributed gain control for DVB-S.2 receiver

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

Design of a 169% locking-range frequency divider with programmable input sensitivity

A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.

A 0.017 µJ/sample 313 K sample/sec clamped sensing-based time domain CMOS temperature sensor

This paper describes the design of a CMOS temperature sensor intended to compensate for the thermal effect of NAND Flash cells. The temperature sensor is mainly composed of a SENSOR part and COUNTER part. The SENSOR part generates a pulse (TPTAT); its width is proportional to absolute temperature (PTAT). Futhermore, the clamped sensing scheme is used to eliminate the effects of temperature and process skew variation of sensing circuits. The COUNTER part converts TPTAT to digital codes. The proposed temperature sensor consumes a 0.017μJ/sample at a conversion rate of 313K sample/sec.

Power transfer characteristics of four-coil magnetic resonance system according to the position of self-resonant coils

The electromagnetic resonance is important candidate of wireless power transfer (WPT) technology for ubiquitous power system. The MIT proposed four-coil WPT scheme based on coupled magnetic resonance. Frequency splitting and critical coupling are shown by distance of resonators. But it is still necessary to assess power transfer characteristics according to various resonator positions.

Coupling effects to power transfer characteristic of resonance four-coil system

In this paper, power transfer characteristics using resonance coupling between four-coils are experimentally shown and compared. Even though each circuit resonates in same frequency, optimum power efficiency is determined by its LC values of source and load due to coupling effects. Optimized four-coil system can achieve the efficiency of over 90% with fixed distance.

A 1.8V wide-band LNA design in 0.18-µm triple-well CMOS

In this paper, comparison between cascode type CMOS low noise amplifiers (LNAs) at different body connection in triple-well structure are presented. By employing a body to source direct connection, the LNA circuit can be designed more compact while maintaining an enhanced gain and bandwidth due to suppression of variation in the threshold voltage. LNAs for DVB-S2 have been designed and fabricated using 0.18-μm triple-well CMOS technology.