Junil Moon

An analysis of magnetic resonance coupling effects on wireless power transfer by coil inductance and placement

This paper presents an analysis of magnetic resonance coupling effects that can be considered for realizing a wireless power transfer (WPT) system. In this study, numerical analysis is applied to investigate the power transfer characteristics affected by coil inductance and placement. The simulations and experiments, using various coils and positions, are conducted to find the optimum power transfer condition. The experiment shows that the frequency bandwidth of the wireless power transfer at the optimum coupling condition is enlarged to 0.73 MHz and the transfer efficiency is maintained at over 80%.

Design of a 5-W power receiver for 6.78 MHz resonant wireless power transfer system with power supply switching circuit

A 6.78 MHz resonant wireless power transfer (WPT) system with a 5 W fully integrated power receiver is presented. A conventional low-dropout (LDO) linear regulator supplies power for operating the circuit in the power receiver. However, as the required operating current increases, the power consumption of the LDO regulator increases, which degrades the power efficiency. In order to increase the power efficiency of the receiver, this work proposes a power supply switching circuit (PSSC). When operation starts, the PSSC changes the power source from the low-efficiency LDO regulator to the high-efficiency step-down DC–DC converter. The LDO regulator operates only for initialization. This chip has been fabricated using 0.18 μm high-voltage bipolar– CMOS–DMOS (double-diffused metal–oxide–semiconductor) (BCD) technology with a die area of 2.5 mm x 2.5 mm. A maximum power transfer efficiency of 81% is measured.

Optimization of resonant inductive links for wireless power transfer

A shunt-series mixed resonant coupled structure for the wireless power transfer (WPT) applications is proposed. If the coils are designed to have proper inductance values, the power transfer efficiency depending on distance has proportional relation only to the shunt capacitors. It enables that the proposed structure facilitates tracking the maximum WPT efficiency according to distance. In the experiment, two pairs of resonant square coils on PCB with different turn ratio (5/10 turn) are compared for 6.78 MHz operation. Both coils have almost same maximum WPT efficiency by optimizing the series and shunt capacitors. But the 10-turn coil only demonstrates aforementioned relation. The proposed structure with 10-turn coil shows that the efficiency of 77.7 % is achieved at a distance of 30 mm.

Investigation of wireless power transfer in multi-coil environment

In this study, simulations and experiments on wireless power transfer (WPT) in a multi-coil environment are conducted under the conditions of multiple battery charging. A series-arrayed 4-coil system comprising one WPT system and three identical WPT systems placed in parallel are investigated in this work. We show that low-frequency wireless power transfer is affected by multiple coils placed in parallel within a confined area. The power transfer efficiency at low frequencies can be degraded by 20% as compared to that of a single WPT system.

A 13.56 MHz CMOS ring oscillator for wireless power transfer receiver system

A 13.56 MHz CMOS ring oscillator for DC/DC converter is demonstrated where measured performances make it suitable for wireless power transfer receiver system. The proposed structure employs a supply-regulated ring oscillator with a temperature compensated current bias circuit, which minimizes the frequency sensitivity to supply and temperature variations. Fabricated in a 0.11 μm 1P5M CMOS process, the developed oscillator as a switching frequency generator of DC/DC converter dissipates maximum 6.8 mW while exhibiting ±0.88 % frequency error against temperature variation of 0-125 °C.

A 12-bit 500-MS/s current steering CMOS DAC for high-speed PLC modems

A 12-bit 500-MS/s current steering digital-to-analog converter (DAC) for high-speed power line communication (PLC) modems is presented in this paper. The performance of current steering DAC is limited by the current cell mismatches and glitch problems caused by switching timing errors. In this paper, the current cell design procedure is presented to minimize random mismatches. Then, a new data-weighted averaging (DWA) technique with fewer glitches and low hardware complexity is proposed to compensate for the gradient mismatch. Spurious-free dynamic range (SFDR) improvement and low complexity are effectively achieved by employing both a row–column structure and a (CSA) structure as the floor plan of the proposed DAC. The proposed DAC is implemented in a standard 0.18-μm CMOS process with an active area of 2.445mm2, which achieves a differential non linearity (DNL) of 0.25LSB and an integral non-linearity (INL) of 0.19LSB. Additionally, the SFDR increases by 13.2dB (on average) when employing the proposed DWA technique. The total power consumption of the proposed DAC is 176mW from a 1.8-V supply voltage.

Design of low-power, fast-transient-response, capacitor-less low-dropout regulator for mobile applications

This paper presents a capacitor-less low-dropout (LDO) regulator for on-chip mobile applications. An additional push-pull current with a capacitive coupling circuit is proposed to significantly enhance the transient response of the LDO regulator. The proposed LDO regulator can deliver an output current of 100 mA with a minimum dropout voltage of 0.4 V. The circuit was modeled and implemented in a 0.35-μm CMOS process with a die area of 0.22 mm. The experimental results show that the LDO regulator can be recovered within 0.5 μs at a voltage spike less than 90 mV.

An inverter layout technique for propagation delay minimization

Through various cases of inverter layout, the change in the propagation delay time (tPD) in the ring oscillator that consists of inverters can be analyzed. In this paper, an inverter layout technique for tPD minimization is presented. Through the case-by-case layout, to reduce the tPD, we propose that layout engineers should reduce the input and output node length. The proposed technique post-simulated in a 0.18um CMOS process achieves maximum 7.318% reduced tPD compared to the basic inverter layout.

Analysis of receiver circuit efficiency for wireless power transfer system according to operating frequency variation

This paper presents a wireless power transfer system for mobile devices. To achieve high efficiency in the receiver circuit, an optimal switching frequency is required. Through experimental analysis, we suggest the optimal efficiency of a receiver circuit. The switching frequency of this receiver circuit can vary from 500 kHz to 13.56 MHz. The received power has a range of 0 to 5 W, and it has a maximum efficiency of 81%. This circuit was fabricated with a 0.18 μm BCD process, and it occupies an area of 2.5 mm × 2.5 mm.

Design of a 169% locking-range frequency divider with programmable input sensitivity

A wide locking-range frequency divider with programmable input sensitivity is presented in this paper. The frequency divider consists of two D flip-flop-based current mode logic latches and a current control circuit. The current control circuit adjusts the current ratio of the sampling pair and the latching pair, while the total current is maintained as a constant. The current control circuit enables the self-oscillation frequency to be adapted to the input frequency. As a result, the divider has wide locking range below -10 dBm input level. The proposed frequency divider is implemented in 0.18 um standard CMOS technology, and the measurement results show a 169% frequency locking range of between 0.5 and 6 GHz at an input power of - 10 dBm while consuming 7.2 mW from a 1.8 V supply voltage.