Hoonki Kim

An Energy-Efficient Fast Maximum Power Point Tracking Circuit in an 800-μW Photovoltaic Energy Harvester

An energy-efficient maximum power point tracking (MPPT) circuit with a fast-tracking time for use with 800-μW PV energy harvesters is presented in this paper. The proposed MPPT circuit uses a successive approximation register MPPT algorithm, which has a power down mode and a fast tracking time, to achieve low power consumption and energy savings. The prototype MPPT circuit, which consists of analog-based circuits, has been implemented and fabricated in a 0.35-μm BCDiMOS process. The MPPT core occupies an area of 3 mm2 and consumes 4.6 μW of power. The tracking time is reduced by 69.4% and the stored energy is increased by 31.4% as compared to the conventional hill climbing-based MPPT algorithm under indoor conditions.

A low power consumption 10-bit rail-to-rail SAR ADC using a C-2C capacitor array

A 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for biomedical applications is presented. The proposed SAR ADC achieves rail-to-rail input range and low power consumption. A Digital-to-Analog Converter (DAC) using C-2C capacitor array and dynamic comparator is used for low power consumption. It is realized in 0.18 mum standard CMOS technology. This ADC has signal to noise and distortion ratios (SNDR) of 53.8dB for 1.5 V supply voltage. It consumes 13.4 muW at sampling rates of 137 kS/s.

A 1-mW Solar-Energy-Harvesting Circuit Using an Adaptive MPPT With a SAR and a Counter

This brief presents an energy-harvesting system that uses an adaptive maximum power point tracking (MPPT) circuit for 1-mW solar-powered wireless sensor networks. The proposed MPPT circuit exploits a successive approximation register and a counter to solve the tradeoff problem between a fast transient response and a small steady-state oscillation with low-power consumption. The proposed energy-harvesting circuit is fabricated using a 0.35-μm CMOS process. The MPPT circuit reduces the transient response time by 76.6%, dissipates only 110 μW , and shows MPPT efficiency of 99.6%.

Low-power programmable divider for multi-standard frequency synthesizers using reset and modulus signal generator

This paper proposes a low-power programmable divider for multi-standard frequency synthesizers using a reset and modulus control signal (RMS) generator. The use of RMS generator enables the adaptation of only one counter. This results in less power consumption and effective area. Our design also includes modified D flip-flop design. Proposed divider was designed and fabricated in a standard 0.18-mum CMOS technology Its divide ratio covers from 13 to 1278 at 3 GHz. The average power is 3.58 mW with 1.5 V power supply and effective area is 0.0408 mm2.

An Energy Efficient

An energy efficient <i>V</i>_PP generator with fast ramp-up time for mobile DRAM is presented in this paper. Instead of using a fixed pumping clock frequency as in the conventional <i>V</i>_PP generator, the proposed <i>V</i>_PP generator adopts a voltage-controlled oscillator (VCO) and uses variable pumping frequencies to improve the ramp-up time as well as energy efficiency. Numerical results show that the VCO based <i>V</i>_PP generators achieve energy savings of up to 34% with 40% improvement on ramp-up time when compared to the conventional ring oscillator (RO) based design. Our proposed <i>V</i>_PP generator, which uses a three-stage voltage doubler as a charge pump, was implemented and fabricated in CMOS 0.13 μm process. The <i>V</i>_PP generator chips core occupies 0.6 mm² area and consumes 1162 nJ (average power of 47.8 mW during 24 μs ramp-up time) while generating 3.0 V output voltage with 1.0 nF load capacitor, 2.0 mA current load and 1.2 V supply voltage.

V_{\rm PP}

A compact, low-power, single-loop third-order delta-sigma (ΔΣ) time-to-digital converter (TDC) for time-mode signal processing is presented in this brief. In general, a high-resolution (ΔΣ) TDC requires a cascadable time integrator to increase the order of the loop filter. However, implementing the time integrator has been very challenging owing to the difficulty in storing time information. In this brief, we present a low-power half-delay time integrator, which is simply composed of two AND gates, a charge pump, and a comparator. The proposed time integrator can be easily cascaded (serially connected) to implement a loop filter with high-order noise shaping. The prototype TDC fabricated in 0.11-μm CMOS process occupies an active area of 0.11 mm2, consuming 0.4 mW from a 1.2 V supply. It achieves the dynamic range of 81 dB over a signal bandwidth of 50 kHz, and the resolution of 4.7 ps over a measurable range of 39.06 ns, which is half the clock period.

Generator With Fast Ramp-Up Time for Mobile DRAM

A 6MHz CMOS reference clock generator is presented in 0.18um CMOS process. The proposed structure adopts a current starved type ring oscillator with low drop out (LDO), and temperature compensated current bias. This structure minimized the effects of supply and temperature to frequency error. The reference clock generator achieves frequency variation of less than ±0.26% against supply variation of 3V ~ 5V and ±0.22% against temperature variation of -20°C ~ 100°C.

A 0.4-mW, 4.7-ps Resolution Single-Loop

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

\Delta \Sigma

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .

TDC Using a Half-Delay Time Integrator

The electromagnetic resonance is important candidate of wireless power transfer (WPT) technology for ubiquitous power system. The MIT proposed four-coil WPT scheme based on coupled magnetic resonance. Frequency splitting and critical coupling are shown by distance of resonators. But it is still necessary to assess power transfer characteristics according to various resonator positions.