Chan Hui Jeong

A 0.31–1 GHz Fast-Corrected Duty-Cycle Corrector With Successive Approximation Register for DDR DRAM Applications

This brief presents a duty cycle corrector (DCC) using a binary search algorithm with successive approximation register (SAR). The proposed DCC consists of a duty-cycle detector, a duty-cycle adjuster, its controller and an output buffer. In order to achieve fast duty-correction with a small die area, a SAR-controller is exploited as a duty-correction controller. The proposed DCC circuit has been implemented and fabricated in a 0.13-μm CMOS process and occupies 0.048 mm2. The measured duty-cycle error for the 50% duty-rate is below 1% (or 10 pS) within 320 pS external input duty-cycle error. The duty of output signal is corrected only with 14 cycles. This DCC operates from 312.5 MHz to 1 GHz and dissipates 3.2 mW at 1 GHz.

An analysis of magnetic resonance coupling effects on wireless power transfer by coil inductance and placement

This paper presents an analysis of magnetic resonance coupling effects that can be considered for realizing a wireless power transfer (WPT) system. In this study, numerical analysis is applied to investigate the power transfer characteristics affected by coil inductance and placement. The simulations and experiments, using various coils and positions, are conducted to find the optimum power transfer condition. The experiment shows that the frequency bandwidth of the wireless power transfer at the optimum coupling condition is enlarged to 0.73 MHz and the transfer efficiency is maintained at over 80%.

All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications

An all-digital duty-cycle corrector with a wide duty correction range and fast correction time is hereby presented. The proposed corrector uses a 1-bit digital duty-cycle detector with a time-to-digital converter, and it achieves a duty correction range between 10% and 90% with a low pressure, volume, and temperature variation. The test chip was fabricated using a 0.13-μm CMOS process, and it occupies an area of 0.059 mm2. The correction cycle is a 14 cycles and the duty-cycle error is below ±1.4%. At an operating frequency of 1 GHz, the power dissipation and peak-to-peak jitter are measured at 5.6 mW and 20.5 ps, respectively.

Investigation of wireless power transfer in multi-coil environment

In this study, simulations and experiments on wireless power transfer (WPT) in a multi-coil environment are conducted under the conditions of multiple battery charging. A series-arrayed 4-coil system comprising one WPT system and three identical WPT systems placed in parallel are investigated in this work. We show that low-frequency wireless power transfer is affected by multiple coils placed in parallel within a confined area. The power transfer efficiency at low frequencies can be degraded by 20% as compared to that of a single WPT system.

A 13.56 MHz CMOS ring oscillator for wireless power transfer receiver system

A 13.56 MHz CMOS ring oscillator for DC/DC converter is demonstrated where measured performances make it suitable for wireless power transfer receiver system. The proposed structure employs a supply-regulated ring oscillator with a temperature compensated current bias circuit, which minimizes the frequency sensitivity to supply and temperature variations. Fabricated in a 0.11 μm 1P5M CMOS process, the developed oscillator as a switching frequency generator of DC/DC converter dissipates maximum 6.8 mW while exhibiting ±0.88 % frequency error against temperature variation of 0-125 °C.

A 6MHz CMOS reference clock generator with temperature and supply voltage compensation

A 6MHz CMOS reference clock generator is presented in 0.18um CMOS process. The proposed structure adopts a current starved type ring oscillator with low drop out (LDO), and temperature compensated current bias. This structure minimized the effects of supply and temperature to frequency error. The reference clock generator achieves frequency variation of less than ±0.26% against supply variation of 3V ~ 5V and ±0.22% against temperature variation of -20°C ~ 100°C.

A wideband cmos cascaded variable gain amplifier using unequally distributed gain control for DVB-S.2 receiver

A fully integrated three stage cascaded radio frequency variable gain amplifier (RFVGA) linearly controlled by exponential current generation circuit is presented. The gain control is unequally distributed in each stage for noise figure (NF) and linearity performance. The dB-linear gain control is realized using pseudo exponential current generated by CMOS current summing circuit with a voltage to current converter. The RFVGA has over 50 dB dynamic range. Gain changes from -38.5 to 16.8 dB according to control voltage that varies from 0.5 to 1.8 V. It operates at 0.95–2.15 GHz. This design is implemented in 0.18 μm CMOS technology.

Digital calibration technique using a signed counter for charge pump mismatch in phase-locked loops

The authors adopt a digital technique to calibrate the current mismatch of the charge pump in phase-locked loops. The proposed digital calibration technique using a signed counter reduces the calibration time up to a minimum of 64% as compared with the other techniques. This technique is designed by a standard 0.18 μm CMOS technology. The calibration time is 32.8 μs, the average power is 6.2 mW at a 1.8 V power supply and the effective area is 0.263 mm 2 .

Design of push-push voltage-controlled oscillator for D-band applications

A D-band push-push voltage-controlled oscillator (VCO) with a constant output power is presented in this paper. A tunable quarter-wave (λ/4) line is proposed to minimize the output power degradation by the mismatch between λ/4 line and the output frequency. The proposed VCO has an oscillation frequency of 120 GHz and a power consumption of 11.0 mW at a supply voltage e of 1.2 V. And it has a minimum output power of -26.0 dBm and the maximum deviation of output power of 1.6 dBm when the tuning range is changed from 115.8 GHz to 126.8 GHz.

Power transfer characteristics of four-coil magnetic resonance system according to the position of self-resonant coils

The electromagnetic resonance is important candidate of wireless power transfer (WPT) technology for ubiquitous power system. The MIT proposed four-coil WPT scheme based on coupled magnetic resonance. Frequency splitting and critical coupling are shown by distance of resonators. But it is still necessary to assess power transfer characteristics according to various resonator positions.