Hyohyun Nam

Study of High-k/Metal-Gate Work-Function Variation Using Rayleigh Distribution

By using a Monte Carlo simulation for the stochastic distribution of grain sizes, the work-function variation (WFV) in high-k/metal-gate (HK/MG) is quantitatively and simply estimated with improved physical validity, with a Rayleigh distribution. Based on the Rayleigh distribution for the grain sizes, the WFV calculation for a TiN gate-stack is validated by previous experimental and simulation results. Additionally, a parameter for the WFV, i.e., ratio of the average grain size to the gate area (RGG), is suggested in this paper. This paves a new path to answer the following questions: 1) to what extent can the grain size of metal-gate materials be minimized to satisfy statistical targets? 2) to what extent can the physical gate area of metal oxide semiconductor field-effect transistors be scaled down whether the total variation is mainly limited by the WFV? Finally, it is concluded that a new HK/MG gate-stack should be developed to have the slope of <; 122 mV in the σ (WFV) versus RGG plot.

Impact of Current Flow Shape in Tapered (Versus Rectangular) FinFET on Threshold Voltage Variation Induced by Work-Function Variation

Depending on the real fin shape in a FinFET (i.e., rectangular versus tapered fin), the impact of the current flow shape in both rectangular and tapered FinFETs on threshold voltage variation induced by work-function variation is investigated by performing extensive 3-D TCAD simulations. It is found that if a FinFET has two independent (versus single and bulky) current flow in the channel, the extended gate area should be (should not be) included in calculating the ratio of average grain size to gate area (RGG) to agree with a previously validated FinFET RGG plot. Depending on the current flow shape in a FinFET, the RGG calculation should be refined.

Study of High-

Because the existing ratio of average grain size to gate area (RGG) method is not applicable for calculating the work function variation (WFV) in nonplanar device structures, a modified RGG method is used to quantitatively estimate the WFV in a high-k/metal-gate (HK/MG) FinFET. A plot of the calculated WFV against the RGG for the FinFET with a TiN gate-stack is validated by previous simulation results. The standard deviation of the WFV, σ(WFV), of the nonplanar multigate device structure (e.g., the FinFET) is lower than that of a planar device structure by ~30%.

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In the past few decades, CMOS logic technologies and devices have been successfully developed with the steady miniaturization of the feature size. At the sub-30-nm CMOS technology nodes, one of the main hurdles for continuously and successfully scaling down CMOS devices is the parametric failure caused by random variations such as line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV). The characteristics of each random variation source and its effect on advanced device structures such as multigate and ultra-thin-body devices (vs. conventional planar bulk MOSFET) are discussed in detail. Further, suggested are suppression methods for the LER-, RDF-, and WFV-induced threshold voltage (VTH) variations in advanced CMOS logic technologies including the double-patterning and double-etching (2P2E) technique and in advanced device structures including the fully depleted siliconon-insulator (FD-SOI) MOSFET and FinFET/tri-gate MOSFET at the sub-30-nm nodes. The segmentedchannel MOSFET (SegFET) and junctionless transistor (JLT) that can suppress the random variations and the SegFET-/JLT-based static random access memory (SRAM) cell that enhance the read and write margins at a time, though generally with a trade-off between the read and the write margins, are introduced.

/Metal-Gate Work Function Variation in FinFET: The Modified RGG Concept

Because of the significantly-increasing work-function variation (WFV) in high-k/metal-gate technology in sub-30-nm nodes, a simple but reasonable model for quantitatively estimating the WFV is currently required. In this study, a Monte Carlo simulation for statistically generating the grain sizes following two different probability distributions (ie Gaussian and Rayleigh distributions) is suggested and performed. The shapes of the grains created by following the Rayleigh distribution (vs the Gaussian distribution) are significantly closer to the real shapes of the grains in the metal gate of TiN. Thus, the WFV estimated by using the Rayleigh distribution is well matched to the previous results.

Analysis of Random Variations and Variation-Robust Advanced Device Structures

A variation-immune symmetric tunnel field-effect transistor (S-TFET) is proposed for the first time to implement bidirectional current flows (ION = 3.6 μA/μm, IOFF = 23 pA/μm at VDD = 0.5 V) with the steep-switching feature of a subthreshold slope (SS) <; 60 mV/dec (SS = 47 mV/dec) and to alleviate the impact of random variation. A random variation analysis with the three major random variation sources, i.e., line-edge roughness, random dopant fluctuation, and work-function variation, is performed to quantitatively evaluate the impact of each variation source on the performance of the device. To perform variation-aware design for the S-TFET, the key device parameter (i.e., the thickness of the intrinsically doped silicon pad layer) is optimized to minimize the impact of random variation on the threshold voltage (VT) and SS. For ultralow power applications with a sub-0.5 V power supply voltage (VDD), the variation-robust S-TFET is one of several promising device structures.

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size

We investigate the impact of metal-interfacial layer-semiconductor source/drain (M-I-S S/D) structure with heavily doped n-type interfacial layer (n+-IL) or with undoped IL on sub-10-nm n-type germanium (Ge) FinFET device performance using 3-D TCAD simulations. Compared to the metal- semiconductor S/D structure, the M-I-S S/D structures provide much lower contact resistivity. Especially, the M-I-S S/D structure with n+-IL provides much lower contact resistivity, resulting in ~5× lower contact resistivity than 1×10-8 Ω-cm2, specified in International Technology Roadmap for Semiconductors. In addition, we found that the M-I-S structure with n+-IL remarkably suppresses the sensitivity of contact resistivity to S/D doping concentration.

Random Variation Analysis and Variation-Aware Design of Symmetric Tunnel Field-Effect Transistor

The work-function variation (WFV) in high-κ/ metal-gate (HK/MG) Ge-source tunnel FETs (TFETs) is evaluated using technology computer-aided design simulations. By matching the simulation results with the plot for the ratio of the average grain size to the gate area (i.e., the RGG plot), we find that the slope in the RGG plot for the TFET can be significantly altered depending on three main factors, namely, the gate width, average grain size, and equivalent oxide thickness. In addition, it is verified that the variation of channel potential affects the WFV-induced threshold voltage variation in HK/MG Ge-source TFETs.

The Efficacy of Metal-Interfacial Layer-Semiconductor Source/Drain Structure on Sub-10-nm n-Type Ge FinFET Performances

Recently, as another pathway of the bulk CMOS scaling, the segmented-channel MOSFET on corrugated substrate was demonstrated. In order to additionally improve its performance, the high-k material (HfO2) in-between the channel stripes of the corrugated substrate as well as in the shallow trench isolation region is used. In this work, the variation-aware design optimization of the SegFET for the LSTP specification is first performed, and then performance, power, variation analysis is followed. The VSTI filled with HfO2 (vs. SiO2) in the corrugated substrate and the STI filled with conventional material (SiO2) demonstrates the best performance, the lowest power consumption, and the least variation in the SegFET.