Jung-Dong Park

A 90 nm CMOS Low-Power 60 GHz Transceiver With Integrated Baseband Circuitry

This paper presents a low power 60 GHz transceiver that includes RF, LO, PLL and BB signal paths integrated into a single chip. The transceiver has been fabricated in a standard 90 nm CMOS process and includes specially designed ESD protection on all mm-wave pads. With a 1.2 V supply the chip consumes 170 mW while transmitting 10 dBm and 138 mW while receiving. Data transmission up to 5 Gb/s on each of I and Q channels has been measured, as has data reception over a 1 m wireless link at 4 Gb/s QPSK with less than 10-11 BER.

A 260 GHz fully integrated CMOS transceiver for wireless chip-to-chip communication

A fully integrated 260GHz OOK transceiver is demonstrated in 65nm CMOS. Communication at 10Gb/s has been verified over a range of 40 mm. The Tx/Rx dual on-chip antenna array is implemented with half-width leaky wave antennas. Each Tx consists of a quadrupler driven by a class-D-1 PA with a distributed OOK modulator, and outputs +5 dBm of EIRP. The Rx uses a double balanced mixer to down-convert to a V-band IF signal that is amplified with a wideband IF driver and demoduated on-chip.

A 0.38 THz Fully Integrated Transceiver Utilizing a Quadrature Push-Push Harmonic Circuitry in SiGe BiCMOS

A fully integrated transceiver operating at 0.38 terahertz (THz) has been demonstrated in 0.13 μm SiGe BiCMOS with fT = 230 GHz. We present a quadrature push-push harmonic circuitry consisting of the clamping pairs driven by balanced quadrature LO signals coupled through the transformers and the Coplanar Stripline (CPS). Harmonic generation of the clamping circuit is analyzed with a clamped sinusoidal model. Several terahertz circuits such as a quadrupler, a THz subharmonic mixer, and an IQ quadrature generator are implemented with the quadrature push-push circuitry to realize a homodyne FMCW radar. Radar functionality is demonstrated with ranging and detection of a target at 10 cm. The measured Equivalent Isotropically Radiated Power (EIRP) of the transmitter is -11 dBm at 0.38 THz and the receiver noise figure (NF) is between 35-38 dB while dissipating a power of 380 mW.

Y-Band On-Chip Dual Half-Width Leaky-Wave Antenna in a Nanoscale CMOS Process

We present a Y-band on-chip half-width leaky-wave antenna for the integrated subterahertz transceiver in a 65-nm digital CMOS process. By utilizing the traveling-wave antenna characteristic, the proposed half-width microstrip leaky-wave antenna (MLWA) structure is concurrently matched to the Rx and Tx, relieving aperture size restriction due to the chip area constraint, while obviating the need for an explicit TR switch. The proposed transceiver (TRx) dual antenna achieves more than 30 GHz of bandwidth (BW), +4.9 dBi of maximum antenna gain, and 26.3% of radiation efficiency at 245 GHz in simulation and measures +5 dBm of maximum equivalent isotropically radiated power (EIRP) with the extremely thin antenna substrate less than 6 μm.

A scalable-low cost architecture for high gain beamforming antennas

Many state-of-the-art wireless systems, such as long distance mesh networks and high bandwidth networks using mm-wave frequencies, require high gain antennas to overcome adverse channel conditions. These networks could be greatly aided by adaptive beamforming antenna arrays, which can significantly simplify the installation and maintenance costs (e.g., by enabling automatic beam alignment). However, building large, low cost beamforming arrays is very complicated. In this paper, we examine the main challenges presented by large arrays, starting from electromagnetic and antenna design and proceeding to the signal processing and algorithms domain. We propose 3-dimensional antenna structures and hybrid RF/digital radio architectures that can significantly reduce the complexity and improve the power efficiency of adaptive array systems. We also present signal processing techniques based on adaptive filtering methods that enhance the robustness of these architectures. Finally, we present computationally efficient vector quantization techniques that significantly improve the interference cancellation capabilities of analog beamforming architectures.

mm-Wave Silicon: Smarter, Faster, and Cheaper Communication and Imaging

This paper will highlight three mm-wave integrated circuit systems appropriate for communication and imaging. The first chip is an efficient transmitter for the realization of a mm-wave system using digital modulation and spatial quadrature power combining. The second system is a prototype 260 GHz short range chip-to-chip communication system in CMOS using on-chip antennas. The final system is a 3D imager with a 90 GHz carrier and 25-parsec pulse width, potentially applicable for HCI (gesture recognition) and medical imaging. These systems represent new application domains for mm-wave electronics where the high volume/low cost of silicon technology can be exploited to realize new functionalities and data rates, addressing important hurdles in the expansion of our communication networks and opening up the ability to see objects in a completely new way using 3D mm-wave imaging.