Sudhir Gowda

A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90-nm CMOS Technology

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feedback equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200mVppd, one transmitter/receiver pair and one PLL consume 300mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization

Integrated transversal equalizers in high-speed fiber-optic systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-/spl mu/m SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-/spl mu/m multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10/sup -5/ to less than 10/sup -12/.

A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS

A 90nm CMOS 10Gb/s SerDes for chip-to-chip communications over backplanes is presented. To mitigate channel impairments, the RX uses a 5-tap DFE and the TX a 4-tap FIR filter. The IC equalization abilities are evaluated using different type of channels. The power consumption of one (TX, RX) pair and one PLL is 300mW for 1.2Vpp differential TX output swing

Improved performance of 10 Gb/s multimode fiber optic links using equalization

A differential 7-tap transverse filter was designed and used to equalize an 850nm multimode link. The ISI penalty was reduced from 11dB to 2.2dB on a l0Gb/s link with 600m of 50/spl mu/m next-generation multimode fiber.

Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization

Differential 4-tap and 7-tap transverse filters are designed in a 0.18/spl mu/m SiGe BiCMOS technology for equalization of 10Gb/s multimode fiber optic signals. The 7-tap equalizer reduced the ISI of a 10Gb/s signal received through 300m of 50/spl mu/m noncompliant next generation multimode fiber from 4.2dB to 0.8dB. The circuit dissipates 40mW from a 3.3V supply.

10+ gb/s 90-nm CMOS serial link demo in CBGA package

We report a 10+ Gb/s serial link demo chip with NRZ signaling in 90-nm CMOS. It consists of a full-rate 4:1 MUX with 8-tap feed-forward equalizer, a half-rate 1:4 DEMUX with programmable peaking pre-amplifier, and a parallel port interface. All coefficients of the 8-tap FIR filter have programmable polarity and magnitude. The chip is housed in CBGA package and has ESD protection devices on all pins. All clock signals are supplied externally. The measured maximum speeds of stand-alone transmitter and receiver are 11.7 Gb/s and 13.3 Gb/s, respectively, and maximum back-to-back operation speed (transmitter + receiver) is 11.4 Gb/s. The chip operates at 10 Gb/s over 20 ft of lossy cable with 20 dB attenuation at 5 GHz. All circuits in the chip use a single 1.0 V power supply, except TX output driver and RX input termination network, which use 1.4 V supply. Total power consumption of TX and RX from the two supplies is 280 mW.

A 30Gb/s 1:4 demultiplexer in 0.12/spl mu/m CMOS

A 1:4 demultiplexer, implemented in 0.12/spl mu/m SOI and bulk CMOS technology, operates with a BER below 10/sup -13/ at 30Gb/s (SOI) and 26Gb/s (bulk) input data rates (2/sup 7/-1 PRBS), drawing 200mA from a 2V supply. At 1.2V, the chips draw 100mA and operates at input data rates of 21Gb/s (SOI) and 18Gb/s (bulk). The design has an active area of 300/spl mu/m /spl times/ 90/spl mu/m.

A 10-Gb/s CMOS clock and data recovery circuit using a secondary delay-locked loop

A 10 Gb/s clock and data recovery (CDR) circuit and a 1:4 DMUX are implemented in 0.12 /spl mu/m CMOS. The CDR employs a secondary wideband delay-locked loop (DLL) to enable independent bandwidth control for jitter transfer and jitter tolerance. The proposed clock recovery and data recovery (CRDR) system enhances the jitter tolerance at high frequencies and offers less data-pattern-dependency for CDRs that use a binary phase detector.

A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.

Circuit and system challenges in IR wireless communication

IR wireless transceivers pose interesting challenges for circuit design. There are two basic types of IR wireless transmission: 1) directed, where the transmitting device must be pointed at the receiver, and 2) diffuse, where the IR signal is emitted into a large solid angle and receiving devices collect the signal reflected off walls and ceiling, thus requiring little or no pointing. Unlike RF, IR schemes employ baseband modulation. At data rates up to 60 kb/s, amplitude shift keying has been used. At higher data rates, RZI or pulse position modulation data encoding schemes (L-PPM where L is the number of slots) are used for more efficient modulation.