Hyun Koo Lee

0.18 um modular triple self-aligned embedded split-gate flash memory

A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.

Influence of underlying interlevel dielectric films on extrusion formation in aluminum interconnects

Knowledge of the mechanical properties of interlevel dielectric films and their impact on submicron interconnect reliability is becoming more and more important as critical dimensions in ultralarge scale integrated circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become more of a concern as the pitches shrink, appear to depend partially on properties of SiO2 underlayers. In this article nanoindentation, wafer curvature, and infrared absorbance techniques have been used to study the mechanical properties of several common interlevel dielectric SiO2 films such as undoped silica glass using a silane (SiH4) precursor, undoped silica glass using a tetraethylorthosilicate precursor, phosphosilicate glass deposited by plasma-enhanced chemical vapor deposition and borophosphosilicate glass (BPSG) deposited by subatmosphere chemical vapor deposition. The elastic modulus E and hardness H of the as-deposited and densified SiO2 layers are measured by nanoi...

High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS Technology

An aggressively scaled high performance 45 nm bulk CMOS technology targeting graphic, gaming, wireless and digital home applications is presented. Through innovative utilization and integration of advanced stressors, thermal processes and other technology elements, at aggressively scaled 45 nm design ground rules, core NFET and PFET realized world leading drive currents of 1150 and 785 uA/um at 100 nA/um off current at IV, respectively. In addition to the high performance transistors, an ultra low-k back-end dielectric (k=2.4) significantly lowers wiring delay. In this technology, CMOS transistors with multiple-oxide thicknesses are supported for low leakage and I/O operations, and competitive SRAM is offered.

The Mechanical Properties of Common Interlevel Dielectric Films and Their Influences on Aluminum Interconnect Extrusions

Knowledge of the mechanical properties of interlevel dielectric films and their impact on sub-micron interconnect reliability is becoming more and more important as critical dimensions in ULSI circuits are scaled down. For example, lateral aluminum (Al) extrusions into spaces between metal lines, which become a more of a concern as the pitches shrink, appear to depend partially on properties of SiO 2 underlayers. In this paper, the mechanical properties of several common interlevel dielectric SiO 2 films such as undoped silica glass using a silane (SiH 4 ) precursor, undoped silica glass using a tetraethylorthosilicate (TEOS) precursor, phosphosilicate glass (PSG) deposited by plasma-enhanced chemical vapor deposition (PECVD) and borophosphosilicate glass (BPSG) deposited by sub-atmosphere chemical vapor deposition (SACVD) were studied. Among the four common interlevel layers, BPSG exhibits the smallest modulus (E), hardness (H) and the highest the coefficients of thermal expansion (CTE). BPSG again has the lowest as-deposited compressive stress and the lowest local Si-O-Si strain before annealing. Stress interactions between the various SiO 2 underlayers and the Al metal film are further investigated. The impact of dielectric elastic properties on interconnect reliability during thermal cycles is proposed.