Rebecca D. Mih

0.18 um modular triple self-aligned embedded split-gate flash memory

A split-gate flash memory cell has been embedded in a 0.18 um high performance CMOS logic process with copper interconnects. A novel triple self-aligned (SA3) process provides a compact cell and high degree of modularity. The entire memory cell structure is defined with one single mask in an area less than 13F/sup 2/. Source-side channel hot electron program and poly-poly tunneling erase enable low power consumption suitable for low voltage applications.

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

Simulations and experiments with the phase-shift focus monitor

Simulation has been used to better understand the process parameters which affect focus monitor performance. Full resist process simulations were done using PROLITH/2. Exposure dose, partial coherence and focus monitor linewidth were varied, assuming an aberration-free lens. The focus monitor result was in good agreement with simulations of two traditional focus test approaches. Simulations were also done with optics having significant third order spherical aberration. In this case, the results of the two traditional focus methods differed with each other, and the focus monitor gave another significantly different result. The focal plane of the aberrated lens depends on what pattern is being printed. Determining the crossing point of focus monitor calibration curves with different partial coherence may allow the lithographic measurement of spherical aberration. This paper also outlines recommendations for the practical use of the focus monitor, along with two examples. The first example illustrates a lens heating problem when using a stepper at a non-standard (sigma) value. The second example demonstrates a focus problem at the edge of the wafer caused by a non-flat chuck.

Phase-shift focus monitor applications to lithography tool control

Through the use of phase shift techniques, focus errors have been demonstrated to result in easily measurable overlay shifts in printed resist patterns. Using box-in-box with phase shifter design, patterns are printed on wafers and measured on standard overlay equipment. Results are compared to more conventional methods of focus detection. Details include measurement and calibration methodology, focus, and focus tilt results. Additionally, SPC in IBMs ASTC Fab is demonstrated with the Phase Shift Focus Monitor.

Using the focus monitor test mask to characterize lithographic performance

The focus monitor technique has been shown to be a unique and promising method of characterizing lithography tools. The focus monitor test mask employs phase shifting to translate focus error into a measurable overlay error, independent of exposure. We have also employed an exposure monitor structure to measure dose, independent of focus. The combination of focus and exposure monitors is highly sensitive to factors which affect critical dimensions. Using this test mask we have systematically analyzed the performance of the photo processing tools on our line. This paper will review the data and discuss process capability improvements using both methodologies.

How focus budgets are spent: limitations of advanced i-line lithography

In order to decide if a given process window is sufficient for volume production without suffering from a significant yield loss, a clear understanding of the process capability is required. Therefore we performed a statistical analysis of all potential contributions for process variations and drifts and evaluated their magnitude for state-of-the-art equipment and processes. Since lithography related fails are not uniformly distributed across the wafer we developed a model to simulate the focus errors across the exposure field and across the wafer. We also developed a yield model, which gives a realistic yield loss number for a given process window. By using these models we show areas of potential improvement, which allow support of processes with significantly less focus latitude. We also investigated field size dependence of focus control and compared the step and repeat and step and scan systems, showing a significant advantage for step and scan systems. All of these findings are not specific to the exposure wavelength, so that they can be easily applied to Deep UV lithography.

Pushing SRAM densities beyond 0.13-μm technology in the year 2000

For any given technology in the logic foundry business it is highly desirable to offer a dense SRAM design which can be manufactured using the same mask and wafer toolsets as the base design. This paper discusses the lithographic issues related to imaging a pseudo-0.11 um technology within a 0.13 um ground rule, including optical proximity correction, design, mask making issues, and comparison of top-down SEM to simulation. To achieve a dense SRAM and quick turn around on design shrinks, simulation and experimental feedback are key. In this study, SRAM cells were redesigned, and a well calibrated resist and etch bias model, in conjunction with a fast micro lithographic aerial image simulator and mask model, were used to predict and optimize the printed shapes through all critical levels. One of the key issues is the ability to correlate and feedback experimental data into the resist simulation. Experimental results using attenuated phase shift masks and state-of-the-art resist process technology are compared to the simulation.

Lithographic implications for Cu/low-k integration

Low dielectric constant materials in the back-end-of-line process are needed to reduce resistive-capacitive delays due to continually shrinking interconnect dimensions. Several organic dielectrics which have etch rates similar to photoresists, such as benzocyclobutene and diamond-like carbon, have been explored for compatibility with lithographic processes. In this paper we discuss integration issues from a lithographic perspective, including low-k materials selection and properties, integration sequences, use of hard masks and the effects on reflectivity, resist process compatibility and focus effects using an advanced DUV scanning system.

Polymer-bound sensitizer in i-line resist formulations

An important component of a photoresist formulation is the photoactive compound. In conventional I-line resist, it is the DNQ molecule. In chemically amplified resists, it is the photoacid generator or the PAG. This component acts as the link between the exposure tool and the photoresist system. While PAGs for the 248 nm or DUV application are plenty, there is little effort in the arena of i-line PAGs. Typically, energy transfer in i-line lithography is achieved by using a DUV PAG in conjunction with an i-line energy transfer agent called sensitizer. This combination works very well, as described by workers before. This paper describes a polymer-bound sensitizer, which while maintaining the performance characteristics of a monomeric sensitizer, also enhances the solubility characteristics and the thermal stability of the resist.