Hyunpil Noh

Electronic and geometric structure of C60 molecules on Au(001)

The electronic and geometric structures of C60 molecular layers on the Au(001) surface were studied by scanning tunneling microscopy (STM) and spectroscopy (STS) and ultraviolet photoemission spectroscopy (UPS). Due to the lattice mismatch between the overlayer C60 and the substrate Au(100)‐(5×20) surface, a uniaxial stress is applied to the overlayer along the 〈110〉 direction, resulting in several types of oblique lattices. The electron charge density around a C60 molecule appears to be an ellipsoid due to the modified electron charge density by the uniaxial stress. The molecules can be considered to be chemisorbed on the Au substrate by the UPS and STS data. Charge transfer from the substrate to the molecules and intermolecular bonding under stress were observed in STM and STS data.

1/2.5" 8 mega-pixel CMOS Image Sensor with enhanced image quality for DSC application

Technology and characteristics of 8-mega density CMOS image sensor (CIS) with unit pixel size of 1.75times1.75mum2 are introduced. With recessed transfer gate (RTG) structure and other sophisticated process/device technology, remarkably enhanced saturation capacity and ultra-low dark current have been obtained, which satisfy the requirements of high density digital still camera (DSC) application

Nano-interconnection for microelectronics and polymers with benzo-triazole

Benzo-Triazole (BTA) is considered as an important bridging material that can connect an organic polymer to the metal electrode on silicon wafers as a part of the microelectronics fabrication technology. We report a detailed process of surface induced 3-D polymerization of BTA on the Cu electrode material which was measured with the Ultraviolet Photoemission Spectroscopy (UPS), X-ray Photoemission Spectroscopy (XPS), and Scanning Tunneling Microscope (STM). The electric utilization of shield and chain polymerization of BTA on Cu surface is contemplated in this study.

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed