Kristof Croes

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Abstract When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Direct observation of the 1/E dependence of time dependent dielectric breakdown in the presence of copper

Time dependent dielectric breakdown (TDDB) lifetime model study has been performed on a metal-insulator-semiconductor capacitor structure with copper directly deposited on silicon dioxide without a barrier material. The structure generates a low electric field acceleration of time-to-failure, which makes it possible to measure TDDB over a wide range of electric fields from 3.5 to 10 MV/cm and experimentally validate TDDB lifetime model without any assumption and data extrapolation. The experimental results are in good agreement with the so called 1/E model and do not support the E, √E, or power-law model.

Impact of post-plating anneal and through-silicon via dimensions on Cu pumping

Irreversible extrusion of Cu from through-silicon vias (TSVs) during high-temperature processing steps presents an important potential back-end-of-line (BEOL) reliability issue. Commonly this reliability risk is mitigated by introducing an anneal after Cu plating for TSV fill. This paper presents the impact of the post-plating anneal temperature and time on residual Cu pumping during a sinter for 20 min at 420 °C, for two different TSV dimensions. Using optical profilometry, in total ~ 4000 TSVs were measured, allowing detailed statistical analysis. Within one sample the Cu pumping values were found to be log normally distributed, implying an intrinsically large spread. Lower residual Cu pumping values were found in TSVs annealed at higher temperatures and for longer times, with the sinter conditions of 20 min at 420 °C confirmed as optimal post-plating anneal conditions. The larger TSVs showed more pumping in the average TSV, but at the tail of the distribution the Cu pumping behavior was the same as for the smaller TSVs. This implies that the impact of Cu pumping on BEOL reliability is identical for both sets of TSV dimensions, suggesting that the impact of Cu pumping on BEOL reliability is not necessarily reduced by reducing TSV dimensions.

Correlation between Cu microstructure and TSV Cu pumping

Cu pumping is the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures during back-end of line (BEOL) processing. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. As potential BEOL reliability issues due to Cu pumping will first occur at the highest pumping TSVs, they can be mitigated if the fundamental cause for this large intrinsic spread is known and under control. This paper describes a clear correlation between Cu pumping and TSV Cu microstructure based on the grain size at the top of 5×50 μm TSV, disregarding twin boundaries. For the mitigation of TSV Cu pumping the ideal microstructure was shown to consist of a single grain spanning the whole TSV cross section, bringing down the highest measured Cu pumping value from 248 nm to 73 nm. This effect was attributed to the absence of rapid diffusion paths and grain boundary sliding ability.

Alternative metals for advanced interconnects

We discuss the selection criteria for alternative metals in order to fulfill the requirements necessary for interconnects at half pitch values below 10 nm. The performance of scaled interconnects using transition metal germanides and CoAl alloys as metallization are studied and compared to conventional Cu and W interconnects.

Low field TDDB of BEOL interconnects using >40 months of data

Over 40 months of low field BEOL TDDB data obtained on different test vehicles with spacings ranging from 90-30nm and OSG low-k dielectrics with k-values ranging from 3.22.0 are summarized. For the dielectrics with k≥2.5, a simultaneous maximum likelihood fit with a fixed acceleration factor and varying distributional shapes is performed. By considering the log-likelihood of each model fit, this approach allows a comparison of fitted lifetime models. This approach also allows estimating the parameters of the impact damage model, which is more difficult to fit due to its multiple acceleration factors. From a statistical point of view and by using a 95% significance level, the results show that the power law and the impact damage model equally outperform all other proposed models and that their prediction to lower fields are very similar. As from a practical point of view the power law model is much more easy to use due to its limited number of fitting parameters, we propose to use the power law model for low-k dielectrics with k-value between 2.5 and 3.2. Regardless of the presence of a protection film, our low-field data obtained on the k=2.0 material show different acceleration factors at high and low fields. This suggests that different breakdown mechanisms are present at different fields and that, in order to allow reliable predictions to operating fields, future TDDB tests of highly porous films will require stresses at much wider field ranges.

Impact of through silicon via induced mechanical stress on fully depleted Bulk FinFET technology

This work provides for the first time an experimental assessment of the impact of thermo-mechanically induced stresses by copper through-silicon vias, TSVs, on fully depleted Bulk FinFET devices. Both n and p type FinFETs are significantly affected by TSV proximity, exhibiting lower impact on drive current with respect to the planar devices. The obtained results are in agreement with the thermo-mechanical models for Cu-TSV and are supported by the 4 point bending stress calibration.

Role of copper in time dependent dielectric breakdown of porous organo-silicate glass low-k materials

The role of copper in time dependent dielectric breakdown (TDDB) of a porous low-k dielectric with TaN/Ta barrier was investigated on a metal-insulator-metal capacitor configuration where Cu ions can drift into the low-k film by applying a positive potential on the top while they are not permitted to enter the low-k dielectric if a negative potential is applied on the top. No difference in TDDB performance was observed between the positive and negative bias conditions, suggesting that Cu cannot penetrate TaN/Ta barrier to play a critical role in the TDDB of porous low-k material.

Copper through silicon via induced keep out zone for 10nm node bulk FinFET CMOS technology

This work provides for the first time comprehensive and early guidelines for TSV integration in 10nm node bulk FinFET technology. The key contributors to the TSV proximity induced Keep Out Zone (KOZ) for FinFET devices are analyzed. Advanced TCAD sub-band modeling of the stress impact on the carrier transport is verified by uniaxial wafer bending experiments. This work provides an analytic compact model to derive first KOZ guidelines for scaled FinFET technologies, introducing the KOZ figure of merit K that directly links to KOZ length and area.

Reliability of MOL local interconnects

From the 32nm CMOS node on, trench shaped local interconnects are introduced to connect the individual transistors on a chip. Aggressive pitch scaling and overlay errors however challenge the integrity of the SiN dielectric between the gate and the local interconnects. In this work we study the reliability of this dielectric. It is found that the current between gate and the contacts is polarity independent and the breakdown voltage shows a strong polarity dependence. While within die good uniformity is observed, due to overlay errors the spacing between the gate and the contact varies across the wafer. This results in large VBD and tBD variability and for an intrinsic TDDB lifetime extrapolation correction for this non-uniformity required.