Ickjin Kwon

A simple and analytical parameter-extraction method of a microwave MOSFET

A simple and accurate parameter-extraction method of a high-frequency small-signal MOSFET model including the substrate-related parameters and nonreciprocal capacitors is proposed. Direct extraction of each parameter using a linear regression approach is performed by Y-parameter analysis on the proposed equivalent circuit of the MOSFET for high-frequency operation. The extracted results are physically meaningful and good agreement has been obtained between the simulation results of the equivalent circuit and measured data without any optimization. Also, the extracted parameters, such as g/sub m/ and g/sub ds/, match very well with those obtained by DC measurement.

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.

An integrated low power highly linear 2.4-GHz CMOS receiver front-end based on current amplification and mixing

A low power 2.4-GHz complementary metal oxide semiconductor (CMOS) receiver front-end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18-/spl mu/m CMOS technology and HP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.

An integrated low power CMOS baseband analog design for direct conversion receiver

A low power CMOS receiver baseband analog (BBA) circuit, based on alternating filter and gain stages, is reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of each block was performed to minimize current consumption. The fully integrated receiver BBA strip is fabricated in 0.18 /spl mu/m CMOS technology and an IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.

A low power highly linear 2.4 GHz CMOS receiver front-end using current amplifier

A low power 2.4 GHz CMOS receiver front end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using a current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18 /spl mu/m CMOS technology and IIP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.

On the large-signal CMOS modeling and parameter extraction for RF applications

A small-signal equivalent circuit of an RF MOSFET not only fully compatible with 4 terminal large-signal quasi-static I-V and Q-V models but suitable for 3 terminal two-port s-parameter measurement, is proposed along with very simple and accurate parameter extraction method. This model includes the intrinsic and extrinsic elements important for AC simulation at RF. The validity and accuracy of our approach is verified from 0.18 /spl mu/m RF NMOS results.

Design of Baseband Analog Chain with Optimum Allocation of Gain and Filter Rejection for WLAN Applications

This paper describes a baseband analog (BBA) chain for wireless local area network (WLAN) applications. For the given specifications of the receiver BBA chain, the optimum allocation of the gain and filter rejection of each block in a BBA chain is achieved to maximize the SFDR. The fully integrated BBA chain is fabricated in 0.13 μm CMOS technology. An input-referred third-order intercept point (IIP3) of 22.9 dBm at a gain of 0.5 dB and an input-referred noise voltage (IRN) of 32.2 nV/√Hz at a gain of 63.3 dB are obtained. By optimizing the allocation of the gain and filter rejection using the proposed design methodology, an excellent SFDR performance of 63.9 dB is achieved with a power consumption of 12 mW.

Corrections to “A Simple and Analytical Parameter-Extraction Method of a Microwave MOSFET”

In the above paper, Ysub in (15) is a function of source–drain capacitance Csd, which itself is obtained from (18) after Ysub has been evaluated. As Csd is a function of both Rsubd and Cjd, which are both, in turn, functions of Ysub, the procedure in this form is not applicable. The j!Csd term is a typographical error and must be omitted from the expression. Thus, in the above paper, (15) should be