Atsushi Hachisuka

A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture

This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 /spl mu/m/sup 2/. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm/sup 2/ for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.

A 143MHz 1.1W 4.5Mb dynamic TCAM with hierarchical searching and shift redundancy architecture

A 4.5 Mb dynamic ternary CAM (DTCAM) is designed in 0.13 /spl mu/m embedded DRAM technology. A performance of 143 M searches/sec is achieved at a power dissipation of 1.1 W and on a small silicon area of 32 mm/sup 2/. A 3.6-times yield improvement is estimated by employing pipelined hierarchical searching and row/column-shift redundancy.

An embedded DRAM hybrid macro with auto signal management and enhanced-on-chip tester

Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TAT) for the various specifications, as well as lower-voltage operation. Conventional eDRAM is generated by placement of hardware macros that are designed beforehand. The hardware macro restricts eDRAM specifications, and many hardware macros are necessary to support the demands of different customers. An eDRAM architecture that provides only the interface component as a software macro, i.e., hardware description language (HDL), has been recently reported. However, in this architecture, adjusting of control signal delays and differing control circuits are necessary for each memory configuration. The architecture reported here provides reduction of design TAT, more than 120 k eDRAM configurations, 1.2 V (100 MHz) to 1.8 V (200 MHz) operation, and a flexible interface. In addition, an enhanced on-chip tester tests the various eDRAM macros, reducing test time to 1/64 with a simultaneous 512 b I/O pass/failjudgment, and performs repair analysis at speed testing conditions.

A 312MHz 16Mb random-cycle embedded DRAM macro with 73/spl mu/W power-down mode for mobile applications

An embedded DRAM macro with self-adjustable timing control and a power-down data retention scheme is described. A 16Mb test chip is fabricated in a 0.13/spl mu/m low-power process and it achieves 312MHz random cycle operation. Data retention power is 73/spl mu/W, which is 5% compared to a conventional one.

A 56.8 GB/s 0.18 /spl mu/m embedded DRAM macro with dual port sense amplifier for 3D graphics controller

Advanced 3D graphics (3DG) technology will be used in console game machines, and it is desired to develop a rendering controller chip which can handle real time 3D animation with true colors. Embedded DRAM (eDRAM) technology attracts attention of the 3DG systems, because only eDRAM can satisfy the required data rate. Four or more pipelines, 200 MHz pipeline operating frequency, and 64 b per pixel are required. With this configuration, the required data rate is 39.4 GB/s, assuming the total penalty of 35% for page miss and video refresh. Furthermore, a 120 Mb frame buffer is required for a 1280/spl times/1024-pixels screen. This 0.18 /spl mu/m 32 Mb eDRAM macro satisfies these requirements.

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros

The voltage margin of an embedded DRAMs sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In this paper, the voltage margin of the sense operation is theoretically analyzed. The accuracy of the proposed voltage margin model was confirmed on a 0.13-μm eDRAM test chip, and the results of calculation were generally in agreement with the measured results.