Tatsunori Murotani

A 30-ns 64-Mb DRAM with built-in self-test and self-repair function

A 64 Mw*1 b/16 Mw*4 b DRAM with 30-ns access time which uses a double-metal layer and 0.4- mu m CMOS technology is reported. The external power supply is 3 V, while memory cell arrays operate at 2.2 V. Key circuits for the 64-Mb DRAM are (1) a latched-sense, shared-sense circuit with open bit-line read-out and folded bit-line rewrite operations (LOF) to reduce inter-bit-line coupling noise, (2) alternatively activated and separately end-located word drivers and X decoders to reduce word-line selection delay, and (3) built-in self test and repair circuits using spare memory cells to reduce test costs and increase chip reliability. >

A 30-ns 256-Mb DRAM with a multidivided array structure

A 256-Mb DRAM with a multidivided array structure has been developed and fabricated with 0.25- mu m CMOS technology. It features 30-ns access time, 16-b I/Os, and a 35-mA operating current at a 60-ns cycle time. Three key circuit technologies were used in its design: a partial cell array activation scheme for reducing power-line voltage bounce and operating current, a selective pull-up data-line architecture to increase I/O width and reduce power dissipation, and a time-sharing refresh scheme to maintain the conventional refresh period without reducing operational margin. Memory cell size was 0.72 mu m/sup 2/. Use of the trench isolated cell transistor and the HSG cylindrical stacked capacitor cells helped reduce chip size to 333 mm/sup 2/. >

A four-level storage 4-Gb DRAM

A 4-Gb DRAM with multilevel-storage memory cells has been developed. This large memory capacity is achieved by storing data at four levels, each corresponding to two-bit-data storage in a single memory cell. The four-level storage reduces the effective cell size by 50%. A sense amplifier using charge coupling and charge sharing was developed for the four-level sensing and restoring. The sense amplifier uses a hierarchical bit-line scheme and operates in a time-sharing mode, thus reducing the sense amplifier area. A 4-Gb DRAM fabricated using 0.15-/spl mu/m CMOS technology measures 986 mm/sup 2/. The memory cell is 0.23 /spl mu/m/sup 2/. Its capacitance of 60 fF is achieved by using a high-dielectric-constant material BST.

A 1-Gb DRAM for file applications

A number of large capacity DRAMs have been developed recently for file applications because data storage devices play an important role in high-speed communication and graphic systems. Such file memories must have low power dissipation, high data transfer rate and low cost. A low chip-yield problem is reported to occur in the manufacture of large capacity DRAMs. To address both device requirements and yield limitations, new circuit technologies have been developed for 1 Gb DRAMs. By implementing a time-shared offset cancel sensing scheme and adopting a diagonal bit-line (DBL) cell, the chip size is reduced to 70% of that of a conventional DRAM. A defective word-line Hi-Z standby scheme and a flexible multi-macro architecture produces about twice the yield as that resulting from conventional architecture. 32 b I/Os with a pipeline circuit technique realizes a 400 MB/s data transfer rate. A 1 Gb DRAM with these features uses 0.25 /spl mu/m CMOS.

A 4-level storage 4 Gb DRAM

Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell reduction technology is needed. Multi-level storage is one circuit technology that can reduce the effective cell size since it allows the storage of multiple voltage levels in a single memory cell functioning as a multi-bit memory. When four levels are stored in a single memory cell, the effective cell size is halved. The authors show that a charge-coupling sense amplifier, charge-sharing restore, and time-shared sensing increase speed and reduce sense-circuit area for 4 Gb DRAM.

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55- mu m CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm/sup 2/ chip area was attained by implementing 4.05- mu m/sup 2/ storage cells. The installed ROM was composed of 18 words*10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm/sup 2/ and the area overhead is about 1%, it proves to be promising for large-scale DRAMs. >

A 3.3 V single-power-supply 64 Mb flash memory with dynamic bit-line latch (DBL) programming scheme

A 3.3 V single-power-supply 64 Mb (4M words x 16b) flash memory with a dynamic bit-line latch (DBL) programming has 50 ns access time and 256 b erase/programming unit-capacity using hierarchical word- and bit-line structures and DBL programming. This memory is fabricated using a 0.4 /spl mu/m-design-rule, double-layer-aluminum, triple-layer-polysilicon, twin-well CMOS technology. To reduce operating voltage, a high-capacitive-coupling ratio (HiCR) cell with high coupling ratio between the control gate and the floating gate is used.<<ETX>>

A boosted dual world-line decoding scheme for 256 Mb DRAMs

A boosted dual word-line decoding scheme with regulated power supply is developed to realize a memory cell applicable to 256 Mb DRAMs by using silicon dioxide as a dielectric material, and without area increase of the memory cell array. The scheme relaxes the wiring pitch on the cell array, thus making it easier to realize wiring patterns in the large step environment caused by the stack capacitor thickness. A capacitance of up to 50 fF can be realized for a dual cylindrical structure with 1 mu m height and 5 mm oxid thickness. The scheme yields word rising operations two times faster than conventional approaches.<<ETX>>

A 55 ns 16 Mb DRAM

The authors describe a 16-Mb CMOS DRAM (dynamic RAM) with 55-ns access time and 130-mm/sup 2/ chip area. It features a high-speed latched sensing (LS) scheme and a built-in self-test (BIST) function with a microprogrammable ROM in which automatic test pattern generation procedures are stored by microcoded programs. To achieve 55-ns access time, the DRAM combines the LS scheme with conventional double-Al-layer wiring and 5-V peripheral circuits. The bit-line sense circuits, driven at 3.3 V from an internal voltage converter to ensure 0.6 mu m MOS memory cell reliability, are shown. Both sensing speed and signal voltage are lower at 3.3 V operation than at 5 V operation. However, the LS scheme compensates for these drawbacks and achieves fast access time and high sensitivity. Operational waveforms for 55-ns row-address-strobe access time for a typical chip under normal conditions are shown, and chip characteristics are summarized.<<ETX>>

A crossing charge recycle refresh scheme with a separated driver sense-amplifier for Gb DRAMs

A crossing charge recycle refresh (CCRR) scheme is proposed for large capacity DRAMs with hierarchical bit-line architecture, which reduces main bit-line charging current to 25% of that of conventional DRAMs. A separated driver sense-amplifier (SDSA) circuit is essential to realize this scheme because it features 11 times shorter charge transfer period than that of conventional sense amplifiers. These circuits are applied to an experimental 1-Gb DRAM.