J. A. Maharrey

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The effects of threshold voltage and body contact are shown to significantly impact the SET response of advanced SOI technologies. Also, the reverse cumulative distribution is extracted from the count distribution for several targets and is shown to be a useful aid in selecting the temporal filtering for radiation-hardened circuitry.

Heavy Ion SEU Test Data for 32nm SOI Flip-Flops

Two 32nm SOI single-event upset test chips have been irradiated at LBNL and TAMU heavy ion test facilities. The test chips include unhardened and RHBD designs such as DICE, LEAP DICE, and stacking devices. SEU cross-section data are presented for the hardened and unhardened flip-flop designs across test facility, beam tune, angle of incidence, and clock frequency.

Utilizing device stacking for area efficient hardened SOI flip-flop designs

D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tilt angle of 55°, and greater than one order of magnitude decrease in cross-section for a heavy-ion tested tilt angle of 75° with less than 50% area penalty compared to unhardened D-flip-flop designs.

Geometry-Aware Single-Event Enabled Compact Models for Sub-50 nm Partially Depleted Silicon-on-Insulator Technologies

A new geometry-aware single-event enabled compact model for sub-50 nm partially depleted silicon-on-insulator MOSFETs is presented. The model extends the bias-dependent single-event modeling methods with an integrated parasitic BJT using the SPICE Gummel Poon equations and parameters derived from the manufacturers process design kit, physical layout, and technology information. The model compares well with TCAD and test data.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

Heavy-Ion Induced SETs in 32nm SOI Inverter Chains

A comprehensive data set of heavy-ion induced single-event transients has been collected for inverter chains fabricated in the IBM 32nm partially-depleted silicon-on-insulator technology across various bias voltages, transistor variants, ion energies and angles of incidence.