T. D. Haeffner

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared to technology computer aided design simulations. A method for compensating for the measurement bias and skew is provided.

The Application of RHBD to n-MOSFETs Intended for Use in Cryogenic-Temperature Radiation Environments

Proton and X-ray irradiation effects are investigated in 0.35 m conventional, annular, and ringed-source radiation-hardening-by-design (RHBD) CMOS devices. Transistors were irradiated with protons at both 300 K and 77 K. Radiation-induced oxide trapped charges in the shallow trench isolation (STI) oxide deplete the p-substrate and effectively shunt the source and drain, inducing off-state leakage. Without the STI, RHBD nFETs exhibit no radiation-induced off-state shunt leakage currents for devices irradiated at both 300 K and 77 K. Conventional 0.35 mum pFETs were not degraded by proton irradiation, since the leakage path cannot be formed in the n-well. A simple CMOS logic inverter shows no degradation in output voltage after proton irradiation for all tested temperature and bias conditions. More advanced 130 nm node nFETs show less TID sensitivity to STI leakage due possibly to the smaller physical STI volume and/or additional doping located on the STI sidewall.

Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling

A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.

Sensitivity of High-Frequency RF Circuits to Total Ionizing Dose Degradation

The combined effects of TID, process corner, and temperature on the performance of high frequency RF circuits are presented. TID experiments at 25°C and 100°C on NMOSFETs and PMOSFETs fabricated in a commercial 45 nm technology show varied degradation in DC and RF performance. The combination of variation due to TID, process, and temperature causes the NMOSFET parameters to fall out of the pre-irradiation process/voltage/temperature (PVT) operating space. TID-aware compact models of MOSFETs are developed based on measured parametric degradation of the transistor behavior. The compact models are used to design a K-band LC voltage-controlled oscillator (VCO), operating at 22 GHz without any compensation circuitry. Circuit simulations show that a 500 krad(SiO2) dose on the VCO operating at 100°C and at the slow process corner can result in circuit failure for biases less than 500 mV. For higher biases, TID causes degradation in frequency, amplitude, and phase noise, causing inability of the VCO to meet the desired performance specifications.

Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology

Isotropic alpha particle single-event upsets (SEU) in flip-flops are characterized over temperature and voltage supply variations in a 20-nm bulk planar complementary metal-oxide semiconductor (CMOS) process. The decrease of the MOSFET drain current in saturation with respect to increased temperature and reduced supply voltage explains the increased SEU sensitivity of the flip-flop designs. Experimental SEU cross sections from isotropic Americium-241, 5.4-MeV alpha particle show irradiation increases by 30 × on average, and up to orders of magnitude, as a result of increased device temperature and reduced supply voltage.

Irradiation and Temperature Effects for a 32 nm RF Silicon-on-Insulator CMOS Process

The impacts of total ionizing dose (TID), temperature and RF stress on the DC and RF performance of a commercial 32 nm RF silicon-on-insulator CMOS technology are presented. Temperature dependence is the overwhelmingly dominant single factor affecting the DC and RF performance, with the combined effects of elevated temperature and TID showing the most pronounced degradation. The most significant effect due to TID is an increase in off-state leakage current. Key DC and RF parameters of this 32 nm RF process degrade less than those of an otherwise similar 45 nm RF SOI CMOS process. The implications of the combined TID and temperature response are discussed for low-power RF design.

Analysis of Bulk FinFET Structural Effects on Single-Event Cross Sections

A set of upset criteria based on circuit characteristic switching time frame is developed and used to bridge transistor-level TCAD simulations to circuit-level single-event (SE) upset cross sections for advanced (fast and small) digital circuits. Interpretation of the measured and 3D TCAD simulated single-event upset (SEU) responses of bulk planar circuits and bulk FinFET circuits using the short-time based upset criteria quantitatively explains the observed divergence of low-LET FinFET cross sections from simple geometric scaling predictions. Comparisons of measured and computed single-event cross section responses show excellent agreement.

Estimating Single-Event Logic Cross Sections in Advanced Technologies

Reliable estimation of logic single-event upset (SEU) cross section is becoming increasingly important for predicting the overall soft error rate. As technology scales and single-event transient (SET) pulse widths shrink to widths on the order of the setup-and-hold time of flip-flops, the probability of latching an SET as an SEU must be reevaluated. In this paper, previous assumptions about the relationship of SET pulsewidth to the probability of latching an SET are reconsidered and a model for transient latching probability has been developed for advanced technologies. A method using the improved transient latching probability and SET data is used to predict logic SEU cross section. The presented model has been used to estimate combinational logic SEU cross sections in 32-nm partially depleted silicon-on-insulator (SOI) technology given experimental heavy-ion SET data. Experimental SEU data show good agreement with the model presented in this paper.

Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology

A 20.4 GHz VCO with a tuning range of 610 MHz (3%) was designed and fabricated in a 32 nm CMOS silicon-on-insulator technology. At 36 °C, the VCO achieves an output power of 0.1 dBm and a phase noise of −99 dBc/Hz at 1 MHz offset from the center frequency. TID experiments on the VCO operating at 36 °C, 75 °C, and 100 °C show degradation in frequency, output power, and phase noise. At 100 °C and 500 krad(SiO2), the VCO shows a worst-case degradation of 630 MHz, 4.3 dBm, and 6.1 dBc/Hz in center frequency, output power, and phase noise, respectively. At 36 °C and up to 500 krad(SiO2), the VCO can be retuned to operate at the required center frequency of 20.4 GHz. However, at 100 °C, the combined effects of temperature and TID result in specification failure. The system-level impact of TID-induced degradation on VCO performance is discussed using a phase-locked loop (PLL) as an example application. Measured performance corroborates previous predictions and highlights the importance of combined effects testing for advanced RF design characterization and qualification.