J. S. Kauppila

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

Impact of Process Variations on SRAM Single Event Upsets

Process variations affect the single event (SE) hardness of SRAM cells. Monte-Carlo simulations show this effect and can be used to quantify the significance of process parameter shifts on SRAM SE upset probabilities.

On-Chip Measurement of Single-Event Transients in a 45 nm Silicon-on-Insulator Technology

Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of measurement-induced uncertainty. SET pulse width data from heavy-ion experiments are provided and compared to technology computer aided design simulations. A method for compensating for the measurement bias and skew is provided.

Circuit-Level Layout-Aware Single-Event Sensitive-Area Analysis of 40-nm Bulk CMOS Flip-Flops Using Compact Modeling

A circuit-level layout-aware single-event simulation capability is presented. Multiple 40-nm bulk CMOS flip-flops are analyzed to determine single-event upset (SEU) sensitive area. Comparisons between simulation results and broadbeam heavy-ion test data show excellent agreement. Simulations of single-event strikes over the entire flip-flop layout can be performed in less than 1 h.

Differential Charge Cancellation (DCC) Layout as an RHBD Technique for Bulk CMOS Differential Circuit Design

A novel RHBD technique utilizing charge sharing to mitigate single-event voltage transients in differential circuits is demonstrated experimentally. Differential charge cancellation (DCC) layout leverages the inherent common-mode rejection of differential circuits to mitigate voltage transients induced by ion strikes. A simple layout variation transforms normally single-ended error signals into common-mode signals that are mitigated by the differential signal path. This layout change maintains the matching achieved via a standard common-centroid layout but incurs negligible area penalty.

Significance of Strike Model in Circuit-Level Prediction of Charge Sharing Upsets

When evaluating sub-100 nm circuits for hardness to Single Event Transients (SETs), the choice of strike model is shown to have a notable effect upon observed upsets. A method utilizing distributed charges to model strikes to adjacent devices is illustrated and utilized to compare the effect of strike kernel models in such Charge Sharing SETS (CSSETS). Bias-dependent models are shown to more accurately predict expected physical observations and Technology Computer Aided Design (TCAD) simulation, especially when such charge-sharing upsets must be considered.

A Comparison of the SEU Response of Planar and FinFET D Flip-Flops at Advanced Technology Nodes

Heavy-ion experimental results were used to characterize single-event upset trends in 16 nm bulk FinFET, 20 nm bulk planar, and 28 nm bulk planar D flip-flops. Experimental data show that 16 nm bulk FinFET flip-flops have considerably lower SEU cross sections than their sub-32 nm planar counterparts for linear energy transfer (LET) less than 10 MeV-cm2/mg. However, FinFET SEU cross section improvement compared to the planar technologies is weak for high LET particles. Three-dimensional technology computer-aided design simulations are used to investigate charge collection mechanisms and single-event transient (SET) pulse widths at these advanced fabrication nodes. Simulation results show that SETs follow conventional scaling trends, which are that SET pulse widths reduce with technology scaling.

RHBD Bias Circuits Utilizing Sensitive Node Active Charge Cancellation

A novel radiation-hardened-by-design (RHBD) technique that utilizes charge sharing to mitigate single-event voltage transients is employed to harden bias circuits. Sensitive node active charge cancellation (SNACC) compensates for injected charge at critical nodes in analog and mixed-signal circuits by combining layout techniques to enhance charge sharing with additional current mirror circuitry. The SNACC technique is verified with a bootstrap current source using simulations in a 90-nm CMOS process. Reductions of approximately 66% in transient amplitude and 62% in transient duration are observed for 60-degree single-event strikes with an LET of 40 MeV*cm2/mg. The SNACC technique can be extended to protect multiple sensitive nodes (M-SNACC). M-SNACC is used to harden the bias circuit of a complementary folded cascode operational amplifier, providing a significant reduction in single-event vulnerability for a 8-bit digital-to-analog converter.

Effect of Device Variants in 32 nm and 45 nm SOI on SET Pulse Distributions

Single-Event Transient (SET) pulse widths were obtained from the heavy-ion irradiation of inverters designed in 32 nm and 45 nm silicon-on-insulator (SOI). The effects of threshold voltage and body contact are shown to significantly impact the SET response of advanced SOI technologies. Also, the reverse cumulative distribution is extracted from the count distribution for several targets and is shown to be a useful aid in selecting the temporal filtering for radiation-hardened circuitry.

Effect of Negative Bias Temperature Instability on the Single Event Upset Response of 40 nm Flip-Flops

Negative bias temperature instability has been experimentally demonstrated to increase the cross-section of the single event response for 40 nm flip-flops. Analysis on the underlying mechanisms, including threshold voltage shift, is presented.