Soo-jin Hong

Electrode dependence of resistance switching in polycrystalline NiO films

We investigated resistance switching in top-electrode/NiO∕Pt structures where the top electrode was Au, Pt, Ti, or Al. For Pt∕NiO∕Pt and Au∕NiO∕Pt structures with ohmic contacts, the effective electric field inside the film was high enough to induce trapping or detrapping at defect states and thus resistance switching. For a Ti∕NiO∕Pt structure with well-defined Schottky contact at Ti∕NiO interface accompanied by an appreciable voltage drop, the effective electric field inside the NiO film was not enough to induce resistance switching. For an Al∕NiO∕Pt structure with a low Schottky barrier at the Al∕NiO interface, resistance switching could be induced at a higher voltage since the voltage drop at the Al∕NiO interface was not negligible but small.

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the densification is. This stress level is proportional to the defect density which is generated in fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

A 20 nm logic device technology for low power and high performance application is presented with the smallest contacted-poly pitch (CPP) of minimal 80 nm ever reported in bulk Si planar device. We have achieved nFET and pFET drive currents of 770 µA/µm and 756 µA/µm respectively at 0.9 V and 1 nA/µm Ioff with the novel high-k/metal (HKMG) gate stack and advanced strain engineering. Short channel effect is successfully suppressed thanks to the optimized shallow junction, resulting in excellent DIBL and subthreshold swing below 120 mV and 90 mV/dec, respectively. In addition, full functionality of SRAM device with 20 nm technology architecture is confirmed.

On the origin of the mobility reduction in bulk-Si, UTBOX-FDSOI and SiGe devices with ultrathin-EOT dielectrics

The effects of ultrathin EOT on the carrier mobility in bulk-Si, UTBOX-FDSOI and SiGe-QW pFET devices were compared. The mobility is found to decrease dramatically with the EOT (Tinv) as a result of stronger charge and surface roughness scattering at thinner SiOx interface layers irrespective of the device technology. UTBOX-FDSOI and bulk-Si nFETs have identical mobility values (190 cm2/Vs) at Tinv=12.5Å. In the UTBOX-FDSOI device architecture, a positive back gate bias provides a strong enhancement in electron mobility. In SiGe-QW pFET devices, a 150% improvement in hole-mobility is observed with low thermal budget laser-anneal (LA).

Void free and low stress shallow trench isolation technology using P-SOG for sub 0.1 /spl mu/m device

Highly reliable void free shallow trench isolation (VF-STI) technology by employing polysilazane based inorganic spin-on-glass (P-SOG) is developed for sub-0.1 /spl mu/m devices. In order to overcome the difficulties from the gap-filling and accumulated mechanical stress in STI, a P-SOG pillar is introduced at the trench bottom. As a result, the P-SOG pillar, having low stress, improves data retention time and hot carrier immunity in 256 Mbit DRAM by reducing cumulative STI stress. In addition, VF-STI shows an excellent extendibility in terms of gap filling capability even at an aspect ratio of more than 10 without void formation.

Highly manufacturable 90 nm DRAM technology

A 90 nm DRAM technology has been successfully developed using 512 Mb DRAM for the first time. ArF lithography is used for printing critical layers with resolution enhancement techniques. A novel gap-filling technology using spin coating oxide is developed for STI and ILD processes. A diamond-shaped storage node is newly developed for large capacitor area with better mechanical stability. A CVD Al process can make the back-end metallization process simple and easy. A dual gate oxide scheme can provide independent optimization for memory cell transistor and periphery support device so that the off-state leakage current of the cell transistor can be maintained below 0.1 fA.

Ultra Shallow Junction Formation Using Plasma Doping and Laser Annealing for Sub-65 nm Technology Nodes

Plasma doping and laser annealing are successfully integrated into the conventional p-metal–oxide–silicon field effect transistor (PMOSFET) process to form ultra shallow junction (USJ). Comparing with the conventional combination of ion implantations and rapid thermal annealing (RTA), junction depth (XJ) and sheet resistance (RS) are reduced. Also, significant improvement of the short channel effects without the degradation of on-current is observed.

Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

The positive bias temperature instability (PBTI) characteristics of the n-channel metal-oxide-semiconductor field emission transistors which had different kinds of high-k dielectric gate oxides were studied with the different stress-relaxation times. The degradation in the threshold voltage followed a power-law on the stress times. In particular, we found that their PBTI behaviors were closely related to the structural phase of the high-k dielectric gate oxide. In an amorphous gate oxide, the negative charges were trapped into the stress-induced defects of which energy level was so deep that the trapped charges were de-trapped slowly. Meanwhile, in a crystalline gate oxide, the negative charges were trapped mostly in the pre-existing defects in the crystallized films during early stage of the stress time and de-trapped quickly due to the shallow energy level of the defects.

Ultrathin gate oxide with a reduced transition layer grown by plasma-assisted oxidation

Ultrathin SiO2 grown by plasma-assisted oxidation (plasma oxide) has been investigated by high-resolution x-ray photoemission spectroscopy and medium energy ion scattering spectroscopy. We found that the plasma oxide grown at the low temperature of 400°C has a thinner transition layer than conventional thermal oxide. This thinner transition layer in the plasma oxide not only decreased the gate leakage current effectively, but also enhanced the reliability of the gate oxide. We attribute these electrical properties of the plasma oxide to the reduction of the transition layer.

Active Width Modulation (AWM) for cost-effective and highly reliable PRAM

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current, ΔIPGM, is reduced from 17.8% to 0.82%, and that of a write energy, ΔEPGM, from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current, IRESET, for sub-40 nm PRAM technology and so on.