J.J. Chang

RTD/CMOS nanoelectronic circuits: thin-film InP-based resonant tunneling diodes integrated with CMOS circuits

The combination of resonant tunneling diodes (RTDs) and complementary metal-oxide-semiconductor (CMOS) silicon circuitry can offer substantial improvement in speed, power dissipation, and circuit complexity over CMOS-only circuits. We demonstrate the first integrated resonant tunneling CMOS circuit, a clocked 1-bit comparator with a device count of six, compared with 21 in a comparable all-CMOS design. A hybrid integration process is developed for InP-based RTDs which are transferred and bonded to CMOS chips. The prototype comparator shows sensitivity in excess of 10/sup 6/ VIA, and achieves error-free performance in functionality testing. An optimized integration process, under development, can yield high-speed, low power circuits by lowering the high parasitic capacitance associated with the prototype circuit.

Microsystem optoelectronic integration for mixed multisignal systems

The integration and packaging of optoelectronic devices with electronic circuits and systems has growing application in many fields, ranging from long to micro haul links. An exploration of the opportunities, integration technologies, and some recent results using thin-film device heterogeneous integration with Si CMOS VLSI and GaAs MESFET circuit technologies are presented. Applications explored include alignment tolerant optoelectronic links for network interconnections, smart pixel focal plane array processing through the integration of imaging arrays with sigma delta analog to digital converters underneath each pixel, and three-dimensional computational systems using vertical through-Si optical interconnections.

Fully differential current-input CMOS amplifier front-end suppressing mixed signal substrate noise for optoelectronic applications

In recent optoelectronic communication systems, microprocessors tend to be imbedded on-chip with analog interface circuitry. This results in a critical substrate noise issues for mixed-signal chip designers because switching transients in digital MOS circuits can interfere with analog circuits integrated on the same die by means of coupling through the substrate. In order to optimize the dynamic range of the system and to minimize the sensitivity to substrate noise, many noise-reduction techniques, such as a P+ guard ring, a N-well guard ring, trench oxide isolation, and MOSCAP have been developed and employed to suppress substrate noise generated by clocking of the digital circuitry in microprocessor. In this paper, a fully differential method is described, which is used to reduce the substrate noise effect caused by the microprocessor. This approach has been implemented in a communications data processing application, in which the microprocessor is located next to the analog current-input optical data receiver and quantization circuits which have a sensitivity of -28 dBm and variable gain characteristic for power efficiency. Both simulated and experimental results of this design approach are presented herein.

Analysis of alignment tolerant hybrid optoelectronic receivers for high density interconnection substrates

High frequency signal distribution in HDI/HDW substrates can be achieved using optical interconnections. To realize effective milli- and micro-haul interconnections on these substrates, the hybrid integration of independently optimized interface circuits and optoelectronic detectors is critical. Further, to realize effective cost goals, designing the optoelectronic interface for alignment tolerance is a key goal. This paper describes the design, fabrication, and test of hybrid integrated optoelectronic interface circuits designed for alignment tolerance and for integration onto an HDI/HDW substrate.

An integrated 155 Mbps digital transmitter using a 1.3 /spl mu/m wavelength thin film LED

This paper reports, for the first time, InP-based thin film surface emitters bonded directly to digital silicon CMOS circuits operating at 155Mbps with digital I/O for application in a three dimensional, through-silicon, communication system. The digital CMOS driver circuitry consisted of a 2-stage tapered buffer, a current switch, and a constant bias current source. The current switch was used before the power transistor stage to avoid voltage spikes. The output stage included a current source to DC bias the LED for increased speed. Careful layout design of the power transistors was performed to minimize any series resistance and to improve the current carrying capability.

Alignment tolerant hybrid photoreceivers using inverted MSMs

We report on the hybrid integration of a thin film large area (250/spl times/250 /spl mu/m/sup 2/, low capacitance (0.43 pF), high responsivity (0.5 A/W, with no AR coating) InGaAs/InP inverted-MSM onto a Si CMOS differential receiver circuit. This integrated receiver demonstrated a bit-error-rate of 10/sup -11/ at 414 Mbps and 0.1/spl times/10/sup -10/ at 480 Mbps. The alignment tolerance of this receiver has been modeled and measured at 200 Mbps, and the theoretical results correspond quite well to experimental data.

Alignment tolerant InP/Si CMOS hybrid integrated photoreceivers operating at 0.9 Gbps

Hybrid integration and alignment tolerant optoelectronic (OE) components are steps toward the realization of low cost, pervasive OE implementation. We report the integration of a thin film large area integrated-MSM onto a differential Si CMOS receiver circuit. This integrated receiver demonstrated operation at 0.9 Gbps and highly alignment tolerant operation at 650 Mbps. Measured alignment tolerance of the receiver corresponded well to the performance predicted by theory.