M. Ueki

A metallurgical prescription for electromigration (EM) reliability improvment in scaled-down, Cu dual damascene interconnects

Electromigration (EM)-derived, void-nucleation and its growth have been investigated in 65-nm node, dual damascene interconnects (DDIs), and the effects of impurity-doping as well as adhesion-strength to SiCN-capping layer (CAP) are discussed regarding the EM-reliability improvement. It is found that reductive surface-treatment of Cu line improves the adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via-bottom. The Al-doping is effective in suppressions both of the void nucleation and the growth, or the drift velocity. Consequently, the Al-doped, dilute Cu-alloy with the strong interface of the Cu/CAP improves the EM lifetime by 50 times refer to that of the conventional pure-Cu. Blocking all migration paths in Cu DDIs is essential for the EM-reliability improvement in 65nm-node LSIs and beyond

Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System

To increase the throughput of electron beam lithography used to fabricate sub-100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conventional KrF stepper. Pattern data preparation was improved for sub-100-nm patterns. To reduce the effect of line width variation caused by post-exposure delay on complementary metal-oxide-semiconductor (CMOS) devices, we first exposed KrF patterns and then added another post-exposure bake before the electron beam (EB) exposure. We have used this technique to expose the gate layer of sub-100-nm CMOS devices. When we set the threshold size between EB and KrF patterns at 0.16 µm, the throughput of electron beam lithography was about threefold that of the full exposure by the electron beam lithography process. Sub-50-nm CMOS devices with high drive current were successfully fabricated.

Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k~2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

Effects of metal-cap coverage on electro-migration (EM) tolerance for scaled-down Cu interconnects

Ultra-high electro-migration tolerant Cu interconnect was achieved by full-coverage metal-cap combined with a porous low-k film having a closed-pore structure such as a molecular-pore-stack (MPS) SiOCH film (k∼2.5). We found that the key feature for the high reliability is “full coverage” of the Cu surface with Co-based metal-cap without Co-penetration into the porous film. The full-coverage metal cap on the pure Cu interconnect improved EM lifetime drastically by “6000 times”, while a partial-coverage metal cap limits the improvement only by 10 times. The interconnect resistance was kept low within +3.2% increment from the pure Cu one, which is far less than that of a Cu-alloy interconnect. Perfect block of the Cu surface-diffusion by the metal cap takes us into another dimension regarding the Cu interconnect reliability, desirable for deeply scaled-down SoCs below 20nm-nodes and/or MCUs under very high temperature environments.

Control of plasma polymerization reaction for the 2 nd generation molecular_pore_stack (MPS) SiOCH film with high deposition rate

To reducing BEOL fabrication cost for 28/20nm-nodes, high-speed process of the low-k deposition is needed under limited equipment investment. By using a standard plasma-CVD equipment with no post-cure process, we have developed high speed deposition technique for a molecular_pore_stack (MPS) SiOCH film from single precursor, which has a hexagonal-silica-ring with hydrocarbon side-chains. Here, the plasma polymerization reaction of the precursors was enhanced simply by controlling the RF power and the gas chemistry with additive gas, which was dissociated itself to increase active charge flux in the plasma. The deposition rate was doubled while keeping the film properties unchanged with the sub-nanometer-size porous structure. No change in the RC performance of the Cu interconnect was observed by using the new MPS film with the high deposition rate. The mechanical properties also were preserved to keep chip-packaging-interaction tolerance.

Highly reliable molecular-pore-stacking (MPS)/Cu interconnects using novel post-etching treatment (PET) for 28 nm-node and beyond

Effects of post-etching treatment (PET) in trench patterning and re-sputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of Molecular Pore Stacking (MPS). Optimized combination of PET and re-sputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times loger EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and re-sputtering, contributes to highly reliability for 28 nm node CMOS and beyond.

Path-finding for integration of porous SiOCH films (k∼2.5) in system-LSIs

Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (Cint) and 8.4%-reduction in propagation delay (rd), which also shrinks the effective variability of zd to improve LSI operation margins. From a viewpoint of BEOL fabrication with k∼2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower Cint than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH.