J. Maniscalco

CVD Co and its application to Cu damascene interconnections

Fundamental material interactions as pertinent to nano-scale copper interconnects were studied for CVD Co with a variety of micro-analytical techniques. Native Co oxide grew rapidly within a few hours (XPS). Incorporation of oxygen and carbon in the CVD Co films (by AES and SIMS) depended on underlying materials, such as Ta, TaN, or Ru. Copper film texture (by XRD) and agglomeration resistance (by AFM) showed correlations with amounts of in-film oxygen/carbon. Cobalt diffused through copper at normal processing temperatures (by SIMS). CVD Co demonstrated diffusion barrier performance to Cu (by Triangular Voltage Sweep, TVS), but not to O2. CVD Co was applied to 32 nm/22 nm damascene Cu interconnect fabrication in a scheme defined by the material studies. Lower post-CMP defect density and longer electromigration lifetimes were obtained.

Effect Of Impurity On Cu Electromigration

The impact of the existence of Cu grain boundaries on the degradation of Cu interconnect lifetime at the 45 nm technology node and beyond has suggested that improved electromigra‐tion in Cu grain boundaries has become increasingly important. In this paper, solute effects of non‐metallic (C, Cl, O and S) and metallic (Al, Co, In, Mg, Sn, and Ti) impurities on Cu elec‐tromigration were investigated. The Cu alloy interconnects were fabricated by adjusting Cu electroplating solutions or by depositing a Cu alloy seed, a thin film layer of impurity, an alloy liner, or a metal cap. A large variation of Cu grain structure in the samples was achieved by adjusting the wafer fabrication process steps. The non‐metallic impurities were found to be less than 0.1% in the electroplated Cu with no effect on Cu electromigration lifetimes. Most of the metallic impurities reduced Cu interface and grain boundary mass flows and enhanced Cu lifetime, but Al, Co, and Mg impurities did not mitigate Cu grain boundary diffusion.

Design and development of high-performance 193-nm positive resist based on functionalized poly(cyclicolefins)

One of the major factors that seem to limit the development of practically useful 193nm resist materials has been their low reactive-ion-etch (RIE) resistance. In this paper, we have shown convincingly that the RIE stability of poly(cyclicolefins) is superior to that of the alternating copolymers such as poly(norbornene-anhydride), and poly(acrylates). We have also shown that a high performance 193nm resist can be developed from functionalized poly(norbornenes) using appropriate formulation and process optimizations.

CVD-Co/Cu(Mn) integration and reliability for 10 nm node

In studying integrated dual damascene hardware at 10 nm node dimensions, we identified the mechanism for Co liner enhancement of Cu gap-fill to be a wetting improvement of the PVD Cu seed, rather than a local nucleation enhancement for Cu plating. We then show that Co “divot” (top-comer slit void defect) formation can be suppressed by a new wet chemistry, in turn eliminating divot-induced EM degradation. Further, we confirm a relative decrease in Cu-alloy seed proportional resistivity impact compared to scattering at scaled dimensions, and finally we address the incompatibility between the commonly-used carbonyl-based CVD-Co process with Cu-alloy seed EM performance This problem is due to oxidation of Ta(N) barriers at the TaN/CVD-Co interface by carbonyl-based CVD processes, which then consumes alloy atoms before they can segregate at the Cu/cap interface. We show that O-free CVD-Co may solve this problem. The above solutions may then enable CVD-Co/Cu-alloy seed integration in advanced nodes.

Robust self-aligned via process for 64nm pitch Dual-Damascene interconnects using pitch split double exposure patterning scheme

A self-aligned via(SAV) process was employed to build 64nm pitch Dual-Damascene(DD) interconnects using a pitch split double exposure pattering scheme to form the Cu lines. TiN hardmask (HM) density and thickness were optimized to achieve the SAV process and DD structure build. We present STEM cross sections of the structures after TiN HM deposition, HM open and DD RIE to determine the minimum required TiN HM thickness for the SAV process. We characterized the TiN loss for each RIE step from cross section results and defined the optimal TiN thickness for 64nm pitch interconnects. Using the optimized TiN thickness, we fabricated DD structures and compared the metal-to-via short electrical performance for SAV and non-SAV processes to show the overlay (OL) impact on shorts yield. Structures fabricated using the SAV process have excellent yield regardless of the degree of via misalignment in the SAV direction since no via CD growth occurs in the constrained SAV direction, while those processed with a non-SAV scheme show via yield degradation with increasing via misalignment. Also, with respect to misalignment in the non-SAV direction, there were no significant electrical differences between structures made using SAV and non-SAV approaches.

Robust and low cost copper contact application for low power device at 32 nm-Node and beyond

We have demonstrated the complete copper filling of contact structures at 32 nm- and 22 nm-node dimensions with the conventional PVD only Ta(N)/Cu barrier/seed process. Copper seed process was optimized to obtain the sufficient coverage of copper along the contact hole with the sufficiently wide gap opening at the top by the use of the directional sputtering and the re-sputtering techniques. In addition, this process was implemented on fully integrated 32 nm-node device wafers and the optimized process produced sufficient performance to meet 32 nm-node requirements. The investigation also included two cases with intentional departure from the optimal conditions, one with a low thickness barrier and the other without copper re-sputtering. In both cases negative influence on front-end-of-the-line (FEOL) parameters was observed.

Pre-liner dielectric nitridation for resistance reduction in copper interconnects

Adhesion tests, parametric measurements, and reliability evaluations of an in-situ pre-liner dielectric nitridation process prior to pure Ta liner deposition were carried out, to evaluate the feasibility of reducing via resistance in BEOL Cu/low-k interconnects. Replacing TaN/Ta with Ta in the conventional liner stack reduces Cu via resistance, while the nitridation treatment maintains Cu interconnect integrity and reliability.

Interactions of Metal-Organic PEALD TaN with Ultra-Low k Dielectric Materials

In order to continue to meet the RC delay requirements of future technology nodes for logic Backend-of-Line (BEOL) interconnect schemes, the successful integration of dual damascene Cu metallization and ultralow k (ULK) dielectric materials with a dielectric constant below 2.7, is projected to be of key importance [1]. Porosity can enable a reduction of dielectric constant values for several classes of low k dielectric materials, into the range of interest for ULK, and hence a variety of porous ULK dielectrics is being evaluated for their performance in BEOL technology [2]. In the area of physical vapor deposition (PVD) Ta(N) barrier technology, tool and process innovations are continually being made to enable barrier scaling for future interconnect dimensions. In this regard, beyond the feature coverage limitations of PVD barriers in general, an additional constraint is starting to present challenges for PVD: deposition rate control. While allowing the formation of highly pure Ta or TaN barrier films, the deposition rates of advanced PVD Ta(N) processes are typically on the order of 1nm/s. For barrier thickness targets in the 1-3nm regime, deposition rate control limitations in PVD may therefore pose considerable reproducibility problems. Alternative process technologies such as chemical vapor deposition (CVD) or atomic layer deposition (ALD) can provide key benefits in terms of deposition rate control and conformality, however, their compatibility with various porous ULK dielectric materials is in doubt [3]. Due to the highly conformal nature of ALD and plasma enhanced ALD (PEALD) processes, nanoscale features can be uniformly coated with ALD films, as demonstrated for PEALD TaN in a trench structure in oxide displayed in Figure 1. The PEALD TaN processes employed in this study are based on the reduction of pentakis(dimethylamino)tantalum (PDMAT) with either a hydrogen plasma or an ammonia plasma. Both these PEALD processes exhibit similar TaN conformality on nanoscale trench structures in oxide, however, the reduction of PDMAT with hydrogen radicals typically leads to the growth of TaN with a lower resistivity. The interaction of hydrogen plasma-based PEALD TaN with patterned dense ULK as well as patterned porous ULK was investigated for organosilicate-based ULK dielectric materials with a dielectric constant of 2.55 (ULK2.55). As observed by scanning transmission electron microscopy (STEM) imaging and energy dispersive X-ray spectrometry (EDX) analysis, no TaN was detected inside the patterned dense ULK2.55 material (Figure 2), while the porous ULK2.55 material exhibited penetration of TaN. It is anticipated that in the latter case, PDMAT diffusion into the pores present in the ULK matrix occurred, and, after adsorption of PDMAT on the inner pore walls, reaction with hydrogen radicals during the plasma exposure steps in the PEALD process lead to the formation of TaN inside the ULK dielectric (Figure 3). Various plasma species can interact differently with the surfaces of porous dielectric materials [4], and therefore the impact of hydrogen plasma-based TaN and ammonia plasma-based TaN on patterned ULK sidewalls was studied for ULK substrates with a dielectric constant of 2.2 (ULK2.2). Moreover, the effect of pore-sealing layers, applied to patterned porous ULK prior to TaN deposition, was evaluated in terms of their ability to reduce TaN penetration into ULK.

Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines

Co/Cu composite interconnect systems were studied. Since wide Cu lines require a diffusion barrier which is simultaneously applied also to fine Co lines to reduce Co volume fraction, through-Cobalt Self-Formed-Barrier (tCoSFB) was employed to thin down TaN barrier to <1 nm which works as an adhesion layer for Co lines. Line R of fine Co lines was reduced by 30% successfully. The Co/tCoSFB-Cu composite interconnect system is promising to achieve low line R for both fine and wide lines simultaneously in 7nm BEOL and beyond.