H. Huang

Experimental study of nanoscale Co damascene BEOL interconnect structures

We characterize integrated dual damascene Co and Cu BEOL lines and vias, at 10 nm node dimensions. The Co to Cu line resistance ratios for 24 nm and 220 nm wide lines were 2.1 and 3.5, respectively. The Co via resistance was just 1.7 times that of Cu, with the smaller ratio attributed to the barrier layer series via resistance. Electrical continuity of Co via chain structures was good, while some chain-chain shorts and leakage suggests metal residuals from the Co polish process. The Co lines and vias, fabricated using conventional BEOL processes, exhibit good Co fill by TEM, with no visible evidence of Co in the dielectric. The relatively smaller resistance increase for Co vias suggests a potential via resistance benefit, a thinner or less resistive barrier can be employed. Co line resistance will likely not be competitive with Cu until after the next technology node.

Ruthenium interconnect resistivity and reliability at 48 nm pitch

48 nm pitch dual damascene interconnects are patterned and filled with ruthenium. Ru interconnect has comparable high yield for line and via macros. Electrical results show minimal impact for via resistance and around 2 times higher line resistance. Resistivity and cross section area of Ru interconnects are measured by temperature coefficient of resistivity method and the area was verified by TEM. Reliability results show non-failure in electromigration and longer time dependent dielectric breakdown. Based on the data collected, Ru could be a metallization contender at linewidth of 16 nm and below.

Microstructure modulation for resistance reduction in copper interconnects

Microstructure variation with post-patterning dielectric aspect ratio (AR) and post-plating annealing temperature has been investigated in Cu narrow wires. As compared to the conventional annealing at 100 ◦C for a feature AR of 2.6, both elevated temperature anneals and reduced AR structures modulated Cu microstructure, which then resulted in a reduced rate of electrical resistivity increase with area scaling and an increased electromigration resistance in the Cu narrow wires.

Electromigration and resistivity in on-chip Cu, Co and Ru damascene nanowires

Electromigration and resistivity of Cu, Co and Ru on-chip interconnection have been investigated. A similar resistivity size effect increase was observed in Cu, Co, and Ru. The effect of liners and cap, e.g. Ta, Co, Ru and SiCxNyHz, on Cu/interface resistivity was not found to be significant. Multilevel Cu, Co or Ru back-end-of-line interconnects were fabricated using 10 nm node technology wafer processing steps. EM in 22 nm to 88 nm wide Co lines, 24 nm wide Cu with and without a thin Co cap and 24 nm wide Ru lines were tested. These data showed that Cu with a Co cap, Co and Ru had highly reliable EM, although Ru was better than Co and Co was better Cu. The electromigration activation energies for Cu with Co cap and Co were found to be 1.5–1.6 eV and 2.1–2.7 eV, respectively.

Comparison of key fine-line BEOL metallization schemes for beyond 7 nm node

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

Cobalt/copper composite interconnects for line resistance reduction in both fine and wide lines

Co/Cu composite interconnect systems were studied. Since wide Cu lines require a diffusion barrier which is simultaneously applied also to fine Co lines to reduce Co volume fraction, through-Cobalt Self-Formed-Barrier (tCoSFB) was employed to thin down TaN barrier to <1 nm which works as an adhesion layer for Co lines. Line R of fine Co lines was reduced by 30% successfully. The Co/tCoSFB-Cu composite interconnect system is promising to achieve low line R for both fine and wide lines simultaneously in 7nm BEOL and beyond.

A novel analytical capacitance model for sub-10 nm interconnects

Quick calculation of capacitance without field solver simulations is desirable to evaluate process assumptions and predict interconnect performance with minimal computation time. At sub-10 nm technology nodes complex interconnect stacks and shrinking dimensions preclude the use of empirical formulae. Here, we extend a physically based quick capacitance model to incorporate sub-10-nm technology elements such as damage layers, multilayer dielectric caps and non-rectangular interconnect cross-sections. The computation time of our model, implemented in standard spreadsheet software is negligible and validation with actual 10-nm node interconnect dimensions shows <;1% error to field solver results. Our model also demonstrates good sensitivity to key process parameters. Our results would be useful to enable quick capacitance estimations for technology and process design.