J. Mazurier

Advances, challenges and opportunities in 3D CMOS sequential integration

3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

In this paper, an in-depth variability analysis, i.e., from the threshold voltage V_T of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local V_T variability σ(V)_T lower than A(V)_T = 1.4 mV · μm is demonstrated. We investigated how this good V_T variability is reported on the SNM fluctuations σ_SNM at the SRAM circuit level. It is found experimentally that σ_SNM is correlated directly to the σ(V)_T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The V_T variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)_T in drive nMOSFETs is the key parameter to control for minimizing σ_SNM.

First demonstration of ultrathin body c-SiGe channel FDSOI pMOSFETs combined with SiGe(:B) RSD: Drastic improvement of electrostatics (V th,p tuning, DIBL) and transport (μ 0 , I sat ) properties down to 23nm gate length

We hereby present for the first time a successful integration of ultrathin (3.2nm) c-Si<inf>0.8</inf>Ge<inf>0.2</inf> layers in Fully Depleted (FD) SOI pMOSFETs (total body thickness: 7.8nm) combined with Si<inf>0.7</inf>Ge<inf>0.3</inf>(:B) Raised Source-Drain. Comparisons with SOI devices show that the c-Si<inf>0.8</inf>Ge<inf>0.2</inf>/SOI channels enable to tune the threshold voltage by +120mV (with excellent variability performance A<inf>Vt</inf>=1.47mV.µm) without SCE or DIBL degradation (60mV/V @ L=23nm). Moreover c-Si<inf>0.8</inf>Ge<inf>0.2</inf>/SOI combined with Si<inf>0.7</inf>Ge<inf>0.3</inf>(:B) RSD leads to significant gain in Access resistance (−60%), transconductance and I<inf>sat</inf> (+170% & +220% @ L=23nm).

High-Performance Ultrathin Body c-SiGe Channel FDSOI pMOSFETs Featuring SiGe Source and Drain:

We report on ultrascaled (LG = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth,p tuning and smart strain management. Indepth electrical characterizations point out the +120-mV Vth,p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% Raccess reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.

V_{\rm th}

For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.

Tuning, Variability, Access Resistance, and Mobility Issues

We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data on both mobility and electrical figures of merit (device and SRAM) offers major opportunities for predictive design based on TCAD simulations.

Improvements in low temperature (&#60;625°C) FDSOI devices down to 30nm gate length

We show that planar Fully Depleted Silicon-On-Insulator (FDSOI) technology allows improving the threshold voltage V_T variability of CMOS devices in comparison to standard bulk CMOS devices. Moreover, integrated on Ultra-Thin Body and Buried oxide (UTBB), it enables the use of standard power management techniques (Reverse or Forward Back Biasing) without V_T variability penalty. Drain current I_D mismatch variations (σ_ID) are found to be correlated with both threshold voltage (V_T) and ON-state resistance (R_ON) fluctuations. Additionally, the impact of R_ON and V_T variations is significantly reduced by their advantageous correlation, while σ_ΔVT remains the major σ_ID contributor. Finally, we demonstrate that SiGe channel could be used to improve global V_T variability of short channel pMOS devices in addition to enhanced performances.

TCAD simulation vs. experimental results in FDSOI technology: From advanced mobility modeling to 6T-SRAM cell characteristics prediction

We demonstrate for the first time that FDSOI technology can be turned into an integrated light-sensitive device technology capable of detecting or interacting with light. By designing a dedicated diode below the BOX, light absorption induced VT shifts as large as 100mV and saturation drain current modulation of 70% are measured for the transistors above the BOX. Those experimental results are supported by TCAD simulations and pave the way to More than Moore applications for FDSOI technology.