J. Roig

Study of novel techniques for reducing self-heating effects in SOI power LDMOS

Abstract Self-heating effects in silicon-on-insulator (SOI) power devices have become a serious problem when the active silicon layer thickness is reduced and buried oxide thickness is increased. Hence, if the temperature of the active region rises, the device electrical characteristics can be seriously modified in steady state and transient modes. In order to alleviate the self heating, two novel techniques which lead to a better heat flow from active silicon layer to silicon substrate through the buried oxide layer in SOI power devices are proposed. No significant changes on device electrical characteristics are expected with the inclusion of the novel techniques. The electro-thermal performance of lateral power devices including the proposed techniques is also presented.

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

Reduction of self-heating effect on SOIM devices

Abstract The silicon-on-insulator (SOI) power devices have an inherent self-heating effect, which limits their operation at high current levels. This is a consequence of the very low thermal conductivity of the thick buried oxide layer. A novel solution to reduce the self-heating effect is proposed in this paper, based on silicon-over-insulator-multilayer (SOIM) emerging technology. A significant reduction of the insulator layer thermal resistance is achieved while keeping constant the electrical behaviour of integrated power devices in comparison to the conventional SOI counterparts. The effectiveness of the proposed solution has been corroborated with numerical simulations. Moreover, no additional steps in fabrication processes are required with regard to the conventional SOI technology.

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.

A 200 V silicon-on-sapphire LDMOS structure with a step oxide extended field plate

Abstract Fabrication of power integrated circuits on silicon-on-sapphire (SOS) substrates has rarely been considered before. Hence, there is a lack of research in lateral power devices integrated on SOS. Self-heating effects in existing silicon-on-insulator (SOI) lateral power devices degrade the device performance and their reliability. Use of SOS substrates could alleviate these problems though they would require a different approach in lateral power device engineering. This paper purposes a new power SOS LDMOS structure with reduced transient self-heating effects and enhanced current capability compared to the conventional SOI counterpart. The proposed lateral power structure integrated on SOS substrates is analyzed by electro-thermal simulations. The field plate is enlarged (extended field plate (EFP)) along the drift region, reaching the drain region. The EFP includes an oxide step which improves the “on-state resistance–breakdown voltage” trade-off (RONxS–Vbr).

Analysis of the breakdown voltage in SOI and SOS technologies

Abstract The aim of the paper is to analyse the breakdown voltage performance of lateral power devices in silicon on insulator (SOI) technologies. Both silicon on oxide (termed SOI as per the convention) and silicon on sapphire (SOS) technologies have been considered. Detailed numerical modelling together with analytical evaluation has been carried out on lateral devices employing uniformly doped and variation in lateral doping drift regions. The results indicate that existing theories to predict breakdown voltage are valid only in the case of ultrathin insulator layers and fail when ultrathick layers are considered. Predicted results for devices with ultrathick dielectric layers, as it is the case in SOS technology, are presented. Moreover, the breakdown voltage sensitivity with respect to the SOI layer and dielectric thickness is also analysed.

Optimisation of very low voltage TVS protection devices

Abstract This paper is aimed at the design and optimisation of advanced Transient Voltage Suppressors (TVS) devices for IC protection against ESD. A four-layer N+P+PN+ structure has been used to achieve breakdown voltages lower than 3 V. The effect of the critical geometrical and technological parameters on the TVS electrical characteristics is analysed with the aid of technological and electrical simulations. In this sense, the trade-off between voltage capability, leakage current and clamping voltage has been optimised. Fabricated TVS devices exhibit better electrical performances than those of the equivalent three-layer TVS device counterparts.

Thin film SOI and SOS LDMOS structures with Linear Doping Profile and enlarged field plate

A new SOS (Silicon-On-Sapphire) LDMOS structure with Linear Doping Profile (LDP), or Variation on Lateral Doping (VLD) in the drift region, suitable for high voltage applications (> 600V) is proposed, analysed and compared with their SOI counterparts in this paper. An Extended Field Plate (EFP) including a step oxide is used to achieve a mirrored SOI-like structure which provides a vertical depletion of the drift region from the field oxide side. The electrical and thermal performances of the proposed structure have been obtained from technological and electro-thermal simulations. Although the subthreshold characteristics of the EFP-SOS LDMOS structure are similar than those of the EFP and FP-SOI counterparts, since the gate region parameters are identical, the blocking voltage and the conduction current capabilities are enhanced. In spite of the lower optimal N/sub d/ value used in EFP-SOS LDMOS transistors, their current capability is higher than that of the EFP-SOI ones due to the significant improvement of the generated heat extraction process.

Thin-film silicon-on-sapphire LDMOS structures for RF power amplifier applications

This work is addressed to the investigation of the electro-thermal performance of RF-LDMOS transistors integrated in TF-SOI, TF-SOS and thinned TF-SOS substrates by means of numerical simulations. Reported experimental trap density, carrier mobility and capture cross-section values have been used together with sapphire datasheet thermal properties, in order to provide accurate simulation results. It is found that subthreshold characteristics are the same for all the analysed substrates while blocking-state, on-state and power dissipation process depends on the substrate type.

Radial confinement in lateral power devices

Abstract The aim of this paper is to demonstrate a novel, radial confinement approach to improve the breakdown performance of a lateral power device. The key feature is that the drift region width decreases gradually from the anode to the cathode to achieve charge confinement in the radial direction. As a result, the n − drift region concentration can be increased by a factor of 7 in comparison to a conventional counterpart leading to a lower specific on-state resistance. This technique is applicable to silicon-on-insulator technologies, such as the SOI or SOS, and to high-voltage thin-film transistor technologies on glass. Experimental results from radial diodes fabricated in SOS technology show a blocking capability higher than from those of their conventional counterparts.