I. Cortés

Analysis of Clamped Inductive Turnoff Failure in Railway Traction IGBT Power Modules Under Overload Conditions

This paper studies the overload turnoff failure in the insulated-gate bipolar transistor (IGBT) devices of power multichip modules for railway traction. After a detailed experimental analysis carried out through a dedicated test circuit, electrothermal simulations at device level are also presented. The simulation strategy has consisted in inducing a current and temperature mismatch in two IGBT cells. Results show that mismatches in the electrothermal properties of the IGBT device during transient operation can lead to uneven power dissipation, significantly enhancing the risk of failure and reducing the lifetime of the power module. Concretely, simulations qualitatively demonstrate that localized hot-spot formation due to a dynamic breakdown could lead to a second breakdown mechanism.

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

The thin SOI TGLDMOS transistor: a suitable power structure for low voltage applications

This paper is addressed to the analysis of the trench gate LDMOS transistor (TGLDMOS) in a thin SOI technology and to investigate its suitability for low voltage power applications. The static and dynamic performances have been extensively analyzed by means of numerical simulations and compared with a conventional thin SOI power LDMOS transistor. The specific on-state resistance of the analyzed TGLDMOS structure is lower than that of the LDMOS counterpart, but the structure design has to be optimized to minimize the added contributions to the parasitic capacitances. In this sense, a modified TGLDMOS is also proposed to reduce the gate–drain capacitance and to increase the frequency capability. The expected electrical performance improvements of both TGLDMOS and modified TGLDMOS power transistors corroborate their suitability for 80 V switching and amplifying applications.

Analysis of low-voltage super-junction LDMOS structures on thin-SOI substrates

This paper is addresses the analysis of the super-junction (SJ) concept applied to LDMOS transistors in thin-SOI technology. Extensive numerical simulations have been carried out to investigate their suitability for low-voltage power applications. The static and dynamic performances of different SJLDMOS structures have been studied in comparison with a conventional RESURF LDMOS structure with the same SOI substrate. In order to improve the current-crowding effect at the body/drift region, the inclusion of a trench lateral gate in the SJ structure (TSJLDMOS) is proposed to further decrease the total on-state resistance (Ron) value maintaining the same voltage capability. The increment of the N+ source and N-drift diffusion area overlapping the gate terminal leads to a gate-related capacitance enhancement. Although very low Ron results can be obtained, the capacitance degradation limits the suitability of TSJLDMOS structure in RF power amplifiers.

Deposited Thin SiO2 for Gate Oxide on n-Type and p-Type GaN

Here, we report on a comparison of two different methods to achieve thin SiO 2 deposited layers for gate oxide on n- and p-type GaN by using plasma-enhanced chemical vapor deposition with silane (SiH 4 ) and tetraethyl orthosilicate (Si[OC 2 H5] 4 ) precursors. An annealing was performed at 800°C for 2 min in N 2 ambient as an attempt to improve electrical characteristics. Before and after annealing, capacitors were electrical/physically analyzed by capacitance-voltage (C-V), conductance-voltage, current-voltage, optical microscope, scanning electron microscope, atomic force microscope, and secondary-ion mass spectrometry. Globally, the p-type samples presented higher interface state density and rougher surfaces, and in some C-V measurements, it is possible to observe inversion-like characteristics. The surface roughness also increases after annealing. The interfacial trap density for the different SiO 2 /GaN interfaces has been determined. Silane samples exhibit lower D it than TEOS samples. For n-type, annealed SiO 2 from silane has been found as the sample with the lowest D it . The annealing on the SiO 2 from silane samples is not so efficient for the p-type with the D it actually increasing. A discussion on the different diffusion mechanisms in correlation with the electrical results is performed in the last section of this paper.

Lateral punch-through TVS devices for on-chip protection in low-voltage applications

A novel lateral punch-through TVS (Transient Voltage Suppressor) structure addressed to on-chip protection in very low voltage applications is reported in this paper. Different lateral TVS structures have been studied in order to optimize the electrical performances related with the surge protection capability. Lateral TVS structures with a four-layer doping profile exhibit the best electrical performances, as in the case of vertical TVS devices. The dependence of the basic electrical characteristics on the technological and geometrical parameters is also analysed. Finally, the electrical performances of lateral TVS structures are compared with those of vertical punch-through TVS devices and conventional Zener diodes, being the leakage current level reduced two orders of magnitude in the case of the lateral architecture. Lateral TVS structures exhibits similar performance than vertical counterparts with the advantage of easiest on-chip integration.

Simulation of Total Ionising Dose in MOS capacitors

Total Ionising Dose (TID) effects are the most important effects of ionising radiation in MOS devices. Among others, TID cause charge trapping in the oxide and in the oxide-semiconductor interface. In this work we develop physical simulation models of charge trapping TID effects in MOS capacitors, in order to have a calculation model for postirradiation experiments. Simulations are made using the Sentaurus TCAD suite, comparing results with well established literature. We calculate the modifications in the C-V curve and the dependence of the flat band voltage due to charge trapping in the oxide, interface traps and the combination of both for increasing dose.

Edge termination impact on clamped inductive turn-off failure in high-voltage IGBTs under overcurrent conditions

This work provides a physical insight into the failure of high-voltage IGBT modules for railway traction when an overload current event occurs during a clamped inductive turn-off. The inspection of failed IGBTs in power modules coming from the field reveals burnt-out points in the vicinity of the device edge termination. This physical signature has been also verified by experimental tests. To explore this result, physical TCAD simulations have been carried out considering, for the first time, the electro-thermal mismatch introduced by the edge termination. From simulation and experimental results, a destructive dynamic avalanche phenomenon at the last IGBT cell is identified as responsible for the observed failure.

Efficiency of SOI-like structures for reducing the thermal resistance in thin-film SOI power LDMOSFETs

Silicon-on-insulator (SOI)-like structures to remove the heat from the active silicon layer in thin-film SOI power lateral double diffused MOS field-effect transistors have been recently reported. This paper provides an experimental demonstration of their efficiency. For this purpose, a heater-sensor system based on poly-Si and platinum resistor stripes, respectively, has been integrated in thermal contact with the active silicon layer under study. The thermal resistance reduction due to the contact-through-buried-oxide technique and the SOI-multilayer substrates have been analyzed at steady state using different SOI layer thicknesses and heat source lengths, in accordance with the state-of-the-art. In addition, experimental results are supported by those extracted from numerical simulation of the heater-sensor system.

On the feasibility of superjunction thick-SOI power LDMOS transistors for RF base station applications

The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for base station applications is studied in this paper. An extensive comparison with conventional RF LDMOS structures is performed in terms of breakdown voltage (VBR) versus drift resistance (Rdr) values. Unlike conventional LDMOS structures, the Rdr value in SJ LDMOS structures not only depends on the doping concentration but especially on the characteristics of P and N pillars. The charge compensation due to inter-diffusion between adjacent pillars is responsible for the observed Rdr increase. In order to accomplish an optimum pillar formation with the minimum possible transition between P and N pillars with inherent net doping reduction, high energy multi-implantations and a small thermal budget must be used. Moreover, the distance between P and N pillar implantation windows must be properly set to alleviate the doping inter-diffusion effect. The VBR/Rdr ratio value is a good indicator to evaluate the SJ LDMOS feasibility for RF applications.