J. Versluijs

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

This paper describes the fabrication process of a fully working 6T-SRAM cell of 0.314/spl mu/m/sup 2/ build with tall triple gate (TTG) devices. A high static noise margin of 172 mV is obtained at 0.6 V operation. Transistors with 40nm physical gate length, 70nm tall & 35nm wide fins, 35nm wide HDD spacer are used. Low-tilt extension/HALO implants, NiSi and Cu/low-k BEOL are some of the key features. This is an experimental demonstration of a fully working tall triple gate SRAM cell with the smallest cell size ever reported.

Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation

For the first time we provide a model for describing the LER induced BEOL TDDB lifetime reduction. The model was validated on 50nm ½ pitch copper damascene lines embedded into a k=2.5 low-k material.

Integration of 20nm half pitch single damascene copper trenches by spacer-defined double patterning (SDDP) on metal hard mask (MHM)

Spacer defined double patterning (SDDP) enables further pitch scaling using 193nm immersion lithography. This work aims to design and generate 20nm half pitch (HP) back-end-of-line test structures for single damascene metallization using SDDP with a 3-mask flow. We demonstrated patterning and metallization of 20nm HP trenches in silicon oxide with TiN metal hard mask (MHM).

Quantifying LER to predict its impact on BEOL TDDB reliability at 20nm ½ pitch

We present results of a refined model that allows prediction of the influence of LER on the TDDB performance when scaling towards 20nm ½ pitch. The model is validated on 35nm ½ pitch state-of-the-art Cu/low-k interconnects, defined in a double patterning integration scheme, using wafer-level TDDB measurements and in-line post-CMP evaluation of both low-k space and parameters describing LER. The results predict a 9 orders of magnitude reduction in TDDB lifetime at 20nm ½ pitch in case uncor-related LER is not scaling, but no further degradation due to protrusions in the dielectric space.

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Abstract. The approach for patterning 15-nm half-pitch (HP) structures using extreme ultraviolet lithography combined with self-aligned double patterning is discussed. A stack composed of a double hard mask, which allows decoupling photoresist transfer and trim, and an α-Si mandrel, which offers better mechanical properties during the mandrel and spacer patterning, is proposed. A break-down study with the patterning steps was performed to investigate the key contributors for improvement of linewidth roughness (LWR), line-edge roughness (LER), and critical dimension uniformity (CDU), targeting integrated solutions with lithography, etch, thin film deposition, and wet cleans for selected applications. Based on the optimization of these key patterning contributors, optimum LWR, LER, and CDU at 15 nm HP are demonstrated.

30-nm half-pitch metal patterning using Motif™ critical dimension shrink technique and double patterning

Double-patterning lithography appears a likely candidate to bridge the gap between water-based immersion lithography and EUV. A double-patterning process is discussed for 30-nm half-pitch interconnect structures, using 1.2 numerical aperture immersion lithography combined with the MotifTM critical dimension (CD) shrink technique. An adjusted optical proximity correction (OPC) calculation is required to model the proximity effects of the Motif shrink technique and subsequent metal hard mask (MHM) etch, on top of the lithography-based proximity effects. The litho-etch-litho-etch approach is selected to pattern a TiN metal hard mask. This mask is then used to etch the low-k dielectric. The various process steps and challenges encountered are discussed, with the feasibility of this approach demonstrated by successfully transferring a 30-nm half-pitch pattern into the MHM.

Contact module at dense gate pitch technology challenges

In this paper we elaborate on challenges faced by contact formation at dense pitch: maintaining gate-to-contact reliability and keeping contact resistance low. We investigate intrinsic and integrated reliability of the gate-to-contact spacing materials and demonstrate capability of nitride gate encapsulation combined with a self-aligned contact etch process to handle misaligned contacts. Resistance of a silicide-through contact process is evaluated on fin substrates.

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.

N5 technology node dual-damascene interconnects enabled using multi patterning

We demonstrate an integration approach to enable 16nm half-pitch interconnects suitable for the 5nm technology node using 193i Lithography, SADP, SAQP, three times Litho-Etch (LE3) and tone-inversion. A silicon-verified DOE experiment on a SAQP process suggests a tight process window for core etch and spacer depositions. We also show a novel process flow which enable us to pattern tight-pitch metal-cut (block), and effectively scale the trench CD to 12nm at pitch 32nm. Finally we discuss line resistance and resistivity obtained for the 16nm and 12nm trenches created using 193i integration flow.

Line Edge Roughness (LER) correlation and dielectric reliability with Spacer-Defined Double Patterning (SDDP) at 20nm half pitch

50% Line Edge Roughness (LER) correlation has been observed after spacer formation in 20nm half pitch (HP) interconnects using Spacer- Defined Double Patterning (SDDP) approach. This correlation has a positive impact on Time-Dependent Dielectric Breakdown (TDDB) lifetime, which was also predicted by simulations. Comparison of TDDB lifetime for SDDP patterned 20nm HP and Litho-Etch-Litho-Etch (LELE) patterned 35nm HP Cu interconnects confirms that the SDDP approach offers potential benefits for TDDB lifetime, which enable future interconnect scaling.