Zs. Tokei

Temperature dependent electrical characteristics of through-si-via (TSV) interconnections

In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25–150°C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped RC model of the TSV for circuit simulations is enhanced by incorporating measured TSV resistance and capacitance change due to temperature. The results are corroborated with the 2D/3D Ring Oscillator (RO) measurements at different temperatures.

Low field TDDB of BEOL interconnects using >40 months of data

Over 40 months of low field BEOL TDDB data obtained on different test vehicles with spacings ranging from 90-30nm and OSG low-k dielectrics with k-values ranging from 3.22.0 are summarized. For the dielectrics with k≥2.5, a simultaneous maximum likelihood fit with a fixed acceleration factor and varying distributional shapes is performed. By considering the log-likelihood of each model fit, this approach allows a comparison of fitted lifetime models. This approach also allows estimating the parameters of the impact damage model, which is more difficult to fit due to its multiple acceleration factors. From a statistical point of view and by using a 95% significance level, the results show that the power law and the impact damage model equally outperform all other proposed models and that their prediction to lower fields are very similar. As from a practical point of view the power law model is much more easy to use due to its limited number of fitting parameters, we propose to use the power law model for low-k dielectrics with k-value between 2.5 and 3.2. Regardless of the presence of a protection film, our low-field data obtained on the k=2.0 material show different acceleration factors at high and low fields. This suggests that different breakdown mechanisms are present at different fields and that, in order to allow reliable predictions to operating fields, future TDDB tests of highly porous films will require stresses at much wider field ranges.

E- and √E-model too conservative to describe low field time dependent dielectric breakdown

Extremely low field time dependent dielectric breakdown measurements were performed on single damascene structures with 90 and 50 nm ½ pitch integrated in a porous low-k material (k=2.5). We found with statistical significance that the E-model and the √E-model were too conservative to extrapolate our high field data to these low fields. Also, while soft breakdown does not occur at higher fields and wider spacings, we demonstrate that the time difference between soft and hard breakdown becomes significant in the 50 nm ½ pitch structures at normal operating fields. Besides this, we detected a change in distributional shape at these low fields and we argue that an extrinsic failure mode could be driving these failures or that the role of spacing variations across the wafer becomes more significant at lower fields.

Holisitic device exploration for 7nm node

In this paper, we review the conditions at which FinFETs could meet system requirements at the 7nm node. We explore the key enablers to meet the power performance targets for 7nm node. We show that the device parasitics is the biggest performance detractor as we scale down. We illustrate the device design space that allows to meet speed and power targets, then explore the optimization of the geometry in combination with disruptive solutions such as air gap spacers and wrapped contacts, the benefits and drawbacks of increased fin height, and the design level solutions such as fin depopulation.

Impact of LER on BEOL dielectric reliability: A quantitative model and experimental validation

For the first time we provide a model for describing the LER induced BEOL TDDB lifetime reduction. The model was validated on 50nm ½ pitch copper damascene lines embedded into a k=2.5 low-k material.

Comparison between intrinsic and integrated reliability properties of low-k materials

Using a dedicated test vehicle (low-k planar capacitor) for studying the intrinsic properties of low-k materials and using standard single damascene 50 and 90nm ½pitch test vehicles, differences in reliability behavior between intrinsic and integrated SiOCH porous low-k materials were investigated. The studied parameters were leakage current, breakdown field, distributional shape of failure times and TDDB lifetimes. Compared to the intrinsic material, the integrated properties significantly deteriorated and these differences were quantified. The low-k planar capacitor test vehicle was also used to study the intrinsic breakdown behavior at low fields. Using statistical simulations, we found that the proper choice of high field conditions is crucial to be able to discriminate between different lifetime models at low fields and recommendations are given on how to choose these high field conditions. Based on tests of several months, the E- and 1/E-model can be excluded (all test material had a standard TaNTa barrier between copper and dielectric). The √E-model and the power law are statistically not different, but a strong tendency towards the power law is observed. As a corollary, we compared the benefit of choosing less conservative lifetime models for extrapolations to lower fields to the loss that occurs when predicting median failure times to lower percentiles. We show that process optimizations leading to a lower spread in the failure times are more important than choosing less conservative lifetime models.

Reliability of copper dual damascene influenced by pre-clean

Copper damascene processing was introduced to reduce circuit speed limiting interconnect RC delays. To prevent copper diffusion into the neighboring dielectric, copper is encapsulated into metallic and dielectric barriers. On the dual damascene level, prior to copper metallization, a pre-clean is applied in order to clean via bottoms. This is necessary to improve yield and decrease via resistance. Conventional preclean employs directional Ar+ bombardment of the wafer surface. This leads to facetting of recess openings and copper sputtering from the underlying metal layer, which is then re-deposited onto recess bottoms. Although several papers detail the impact of pre-clean on via resistance none of them treats in detail the eventual issues related to copper re-deposition underneath the metallic barrier in direct contact with the dielectric. The present paper shows how conventional pre-clean can influence Cu+ drift rate due to copper re-deposition, plasma damage and via resistance.

Barrier/liner stacks for scaling the Cu interconnect metallization

Self-forming barriers and advanced liner materials are studied extensively for their Cu gapfill performance and interconnect scaling. In this paper, 22nm1/2 pitch Cu low-k interconnects with barrier (Mn-based, TaN) /liner (Co, Ru) combinations are compared and benchmarked for their resistivity, resistance scaling, and electromigration (EM) performance. Extendibility to 16nm copper width was explored experimentally and a projection towards 12nm width is performed. It is found that the Ru-liner based systems show a higher overall Cu-resistivity. We show that this increase can be compensated by combining Ru with a thinner Mn-based barrier, which increases the effective Cu-area at a particular trench width. The EM performance reveals that the Ru-liner systems have a better EM lifetime compared to the Co-liner based systems. More interestingly, in a comparison of the maximum current density Jmax a significant improvement is found for the scaled Mn-based/Ru system, making it therefore a serious candidate to extend the Cu metallization.

Lateral versus vertical gate-all-around FETs for beyond 7nm technologies

Nominal LG VFET-based RO may operate up to ~60% faster than LFET-based RO at the same energy per switch for both 7nm and 5nm technology nodes depending on the layout and BEOL-load. With VFETs, relaxing the LG is possible and it results in an extra 27% in IEFF in comparison to the nominal LG case. In addition, VFETs enable different layouts, which can be used to optimize performance under certain BEOL-load. Introduction of VFETs is more favorable at the 5nm node than at the 7nm node. As such, VFETs show a performance competitive path for continued scaling beyond 7nm technologies.

Impact of copper contacts on CMOS front-end yield and reliability

With copper contact technology, CMOS front-end yield and reliability are governed by the quality of the contact barrier stack. Poor barrier quality gives rise to yield loss in junctions and gate dielectrics, and reduced time-to-breakdown with characteristic breakdown signature. Failure analysis reveals the presence of copper silicide as the underlying cause, its impact depending on the exact location of the affected region. With optimized barrier there is no indication for copper related front-end yield and reliability problems