Jaesung Sim

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A NAND-type MONOS device has been successfully developed by breakthrough technologies including optimized cell structures and integration schemes providing favorable memory cell structures and peripheral circuits. In this study, optimized TANOS (TaN-Al2O 3-nitride-oxide- silicon) cells integrated using 63nm NAND flash technology showed high performance compatible to floating-gate (FG) cell. The newly-developed TANOS-NAND flash technology proved to be a promising candidate to replace FG memory beyond 50nm technology

Highly Manufacturable 32Gb Multi -- Level NAND Flash Memory with 0.0098 μm 2 Cell Size using TANOS(Si - Oxide - Al2O3 - TaN) Cell Technology

A highly manufacturable 32Gb multi-level NAND flash memory with 0.0098 μm2 cell size using 40nm TANOS cell technologies has been successfully developed for the first time. The main key technologies of 40nm 32Gb NAND flash are advanced high N.A immersion photolithography with off-axis illumination system, advanced blocking oxide of the TANOS cell, and PVD tungsten and flowable oxide for bit line

Effects of Lateral Charge Spreading on the Reliability of TANOS (TaN/AlO/SiN/Oxide/Si) NAND Flash Memory

It was found that the charge loss behavior of TANOS (TaN-Al2O3-nitride-oxide-silicon) cells for NAND flash memory application is highly dependent on the gate structures for the first time. The gate structures with trap layers remained on source and drain regions showed increased charge loss compared to the one with trap layers separated between different gate lines. The improvement by removing the trap layers between gate lines suggests that the lateral charge spreading via trap layers from the programmed cells to the adjacent erased cells contributes to the charge loss of the TANOS cells.

Multi-Level NAND Flash Memory with 63 nm-Node TANOS (Si-Oxide-SiN-Al2O3-TaN) Cell Structure

For the first time, multi-level NAND flash memories with a 63 nm design rule are developed successfully using charge trapping memory cells of Si/SiO2/SiN/Al2O3/TaN (TANOS). We successfully integrated TANOS cells into multi-gigabit multi-level NAND flash memory without changing the memory window and circuit design of the conventional floating-gate type NAND flash memories by improving erase speed. The evolved TANOS cells show four-level cell distribution which is free from program disturbance and a charge loss of less than 0.4 V at high temperature bake test

A 64-Cell NAND Flash Memory with Asymmetric S/D Structure for Sub-40nm Technology and Beyond

A new 64-cell NAND flash memory with asymmetric S/D (Source/Drain) structure for sub-40nm node technology and beyond has been successfully developed. To suppress short channel effect in NAND memory cell, asymmetric S/D consisting of optimized junction and inversion layer induced by fringe field of WL bias which is applied at NAND operation conditions is successfully utilized. 64-cell NAND string which is double number of cells used in current NAND string is also used to further reduce bit cost by achieving over 10% chip size reduction while almost maintaining MLC (multi-level-cell) NAND performance requirements

Data Retention Characteristics of Nitride-Based Charge Trap Memory Devices with High-

The data retention characteristics of nitride-based charge trap memories using metal–oxide–nitride–oxide–silicon (MONOS) structures employing high-k dielectrics and high-work-function metal gates have been investigated. The fabricated MONOS devices with structures of TaN/Al2O3/Si3N4/SiO2/ p-Si show fast program/erase characteristics with a large memory window of greater than 6 V at program and erase voltages of ±18 V. From a bake retention test at high temperatures (200, 225, 250, and 275 °C), it is expected to take more than 40 years to lose less than 0.5 V charge loss at 85 °C. In this paper, we present an optimized cell structure for both improved data retention and erase speed, as well as a systematic study on the charge decay process in MONOS-type flash memory for high-density device applications.

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To realize TANOS-NAND flash memory, key requirements like program/erase speed, read retention, and program disturb window should be satisfied. In this work, we present 63 nm NAND-type TANOS cells to satisfy all the requirements and to replace floating-gate cells in conventional NAND flash memory without changing a circuit design and a sensing window

Dielectrics and High-Work-Function Metal Gates for Multi-Gigabit Flash Memory

Silicon/metal-oxide-nitride-oxide-silicon (SONOS/MONO S) devices receive increasing interest recently due to their simpler process, smaller cell size, and better endurance over the floating-gate devices [1]. However, charge retention and erase speed remain as the major challenges for SONOS devices to replace floating-gate devices [1,2]. Recently, it is reported improved erase performance and endurance characteristics can be achieved by replacing SiO2 and poly-Si as high-k dielectric, Al2O3 and high-work function metal, TaN for blocking oxide and gate material, respectively [3]. However, data retention characteristics still need to be improved since memory window is very small after long time retention. In this work, we present an optimized cell structure for both improved data retention and erase speed in SONOS-type flash EEPROM.

Charge Trapping Memory Cell of TANOS (Si-Oxide-SiN-Al2O3-TaN) Structure Compatible to Conventional NAND Flash Memory

In this article, we demonstrate successful integration of selective epitaxial growth (SEG) contact for high density NAND flash memory devices. For high transistor breakdown voltage of a scaled high voltage (HV) transistor, SEG process was adopted to prepare for elevated doped region. It was found that the plug ion implantation (IIP) as a key step should be differently applied to HV transistor region and cell region. By employing optimized SEG contact in scaled NAND flash devices, HV transistor breakdown voltage, comparable Id-Vg characteristics, body effect, shut off and isolation characteristics were obtained without any noticeable degradation of cell characteristics. Introduction For the past 10 years, much effort has been dedicated to scale NAND flash memory devices [1, 2]. However, even with various junction structures such as lightly doped drain (LDD) structure and DDD (doubly doped drain) structure [3, 4], the aggressive scaling of HV transistor was a formidable task. There are limits on manufacturing more highly integrated devices capable of resisting high voltages using such junction structures. To overcome a short channel effect, the scaling of a low concentration junction depth causes the degradation in junction breakdown. To obtain high junction breakdown, an effective area of the high concentrated diffusion layer should be increased. An elevated source and drain technology has thus been developed with an epitaxial layer formed on a substrate and impurities being implanted into the epitaxial layer [5]. In our study, we address a successful integration of the SEG process into HV transistor fabrication for high density NAND flash with design rule of 63nm and beyond. Experimental Fig. 1 shows the integration scheme to implement SEG process for HV transistor contact and cell bit line contact in 63nm technology. After gate stack processes, all devices were capsulated by inter-dielectric, followed by forming contact holes by dry etch process. Then, SiN sidewall spacers of contact holes were formed to increase the growth rate of the subsequent epitaxial layer. Plug IIP was performed on the only cell region because of different requisite of plug IIP for peripheral HV transistor region and cell region. Afterward, the epitaxial layer in both regions was deposited simultaneously by SEG method, followed by IIP on epitaxial layer. As a contact metal and bit line material, W layer was subsequently deposited and patterned. Results & Discussion Fig. 2 compares device structures of a conventional HV transistor with doped poly-Si direct contact (DC) and a novel HV transistor with SEG contact. By implementing elevated source and drain by SEG, the lateral distance from gate to contact can be decreased from A (conventional HV Tr.) to B (novel HV Tr.). Fig. 3 shows the simulation results of gate induced drain leakage (GIDL) current of conventional HV Tr., and novel HV Tr. Compared to a conventional HV Tr., a novel HV Tr. device shows reduced GIDL at high drain bias, resulting in improved transistor breakdown voltage because of the increased effective gate to contact distance from A to A plus α. Fig. 4 & 5 show different requirements of plug IIP for HV transistor region and cell region. There is little difference between a conventional HV device with plug IIP plus doped poly-Si DC and a novel HV device with plug IIP plus SEG contact. However, the novel HV device without plug IIP process shows high transistor breakdown voltage up to 3.7V. Therefore, the plug IIP should be skipped for HV device with SEG contact. However, in terms of worst-on-cell-current, plug IIP prior to SEG process is favorable. Fig. 6 shows the Id-Vg characteristics of a novel HV Tr. with IIP dose on top of the epitaxial layer. In our experiments, IIP condition was variously optimized. The current characteristics of optimized SEG contact were comparable to conventional one at the same effective gate to contact distance (lateral plus vertical). Fig. 7 shows high transistor breakdown voltage characteristics for SEG contact device regardless of the distance from gate poly to contact without any degradation of other electrical characteristics including body effect in Fig. 8, virgin Vth, shut off and isolation characteristics (not shown). Fig. 9 shows the junction characteristics implemented by conventional DC and SEG contact. The SEG contact shows lower junction leakage and higher breakdown voltage, which can be explained by the increased resistive layer. Fig. 10 shows measured worst-on-cell-current of SEG contact device and conventional contact device with Vread of 5.5V, and 6V. No degradation was observed in the measured worst-on-cell-current at Vread of less than 5.5V. Considering of low Vread condition for multi level, the measured worst on cell current at 5.5V is acceptable. Summary In our study, we address a successful integration of SEG process into HV transistor fabrication for high density NAND flash process technology with design rule of 63nm and beyond. For high transistor breakdown voltage of a scaled HV transistor, SEG process was adopted to prepare for elevated doped region. The plug IIP as a key step should be differently applied to HV transistor region and cell region. By employing optimized SEG contact in a scaled HV transistor, high transistor breakdown voltage, comparable Id-Vg characteristics, body effect, shut off and isolation characteristics were obtained without any noticeable degradation of cell characteristics. References [1] K. Kim et al., IEDM, pp.333-336 (2005) [2] J-H. Park et al., IEDM, pp 873-876 (2004) [3] H. Mikoshiba et al., IEEE TED, pp.140-144 1986 [4] K, Balasubramanyam et al., IEDM pp. 121-135 1984 [5] M. Park et al., US patent currently pending Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -560P-4-4 pp. 560-561

Data Retention Characteristics of MONOS Devices with High-k Dielectrics and High-work Function Metal-gates for Multi-gigabit Flash Memory

We present the TANOS (Si-Oxide-SiN-Al 2 O 3 -TaN) cell with 40 A-thick tunnel oxide erased by Fowler-Nordheim (FN) tunneling of hole. Thanks to introducing high-k dielectrics, alumina (Al 2 O 3 ) as a blocking oxide, the erase threshold voltage can be maintained to less than - 3.0 V, meaning hole-trapping in SiN. We extracted the nitride trap densities of electron and hole for the TANOS cell. It is demonstrated that the TANOS structure is very available to investigate the trap density with shallower energy. The energy level of hole trap (1.28 eV) is found to be deeper than that of electron (0.8 eV). As the cycling stress is performed, persistent hole-trapping is observed unlike endurance characteristics of conventional floating-gate cell. The hole trapping during the cycling stress can be attributed to two possibilities. The injected holes are trapped in neutral trap of tunnel oxide and residue of holes which is not somewhat compensated by injected electrons may be accumulated in SiN. It is demonstrated the erase operation of the TANOS cell is governed by Fowler-Nordheim tunneling of hole due to the field concentration across the tunnel oxide.