Jefy Jayamon
University of California, San Diego
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Publication
Featured researches published by Jefy Jayamon.
IEEE Journal of Solid-state Circuits | 2014
Amir Agah; Jefy Jayamon; Peter M. Asbeck; Lawrence E. Larson; James F. Buckwalter
Gate resistance significantly limits the output power and power-added efficiency of stacked-FET power amplifiers in 45 nm SOI CMOS above 60 GHz. A multi-drive stacked-FET approach is proposed to improve the output power and efficiency. An analysis of conventional and multi-drive stacked-FET PAs demonstrates the performance improvement. A multi-drive three-stack PA is implemented in 45 nm SOI CMOS for 90 GHz operation occupying 0.23 mm 2 . This PA achieves more than 19 dBm output power with peak PAE of 14% and 12 dB gain at 90 GHz using a 3.4 V power supply.
radio frequency integrated circuits symposium | 2014
Jefy Jayamon; Ozan Dogan Gurbuz; Bassel Hanafi; Amir Agah; James F. Buckwalter; Gabriel M. Rebeiz; Peter M. Asbeck
A spatially power-combined CMOS SOI power amplifier at 94 GHz is reported. The CMOS chip contains a 2×4 array of pseudo-differential power amplifiers, and is integrated with a microstrip antenna array on a quartz superstrate. A 13-stage amplifier chain is implemented to provide gain, using stacked NFETs in a 45-nm CMOS SOI process. The amplifier array outputs a power of 24 dBm (250 mW) and the chip-quartz assembly radiates an equivalent isotropic radiated power (EIRP) of 33 dBm at 94 GHz. This is the highest radiated power reported from a Silicon CMOS active array transmitter at W-band, and the highest W-band output power from a single CMOS chip.
international microwave symposium | 2013
Amir Agah; Jefy Jayamon; Peter M. Asbeck; James F. Buckwalter; Lawrence E. Larson
A two-stage 90-GHz stacked-FET power amplifier is implemented in 45-nm SOI CMOS. Dual supply operation supports high gain, power and efficiency in the two-stage design. The amplifier exhibits greater than 15.8 dBm saturated output power with 10 dB peak power gain and achieves a record peak PAE of 11%. The PAE remains above 8% from 86 to 94 GHz. It occupies 0.05 mm2 excluding pads.
radio and wireless symposium | 2013
Jefy Jayamon; Amir Agah; Bassel Hanafi; Hayg Dabag; James F. Buckwalter; Peter M. Asbeck
A 90GHz power amplifier implemented with three series-connected (stacked) FETs in 45-nm SOI CMOS is reported. Stacking FETs allows increasing voltage handling capability of circuits with highly scaled CMOS transistors. This work shows for the first time that the stacking strategy is effective up to W band. The amplifier achieves power gain of 8 dB at 91 GHz with 3 dB bandwidth of 18 GHz using a supply voltage of 4.2 V. It delivers saturated output power of 17.3 dBm in 88-90 GHz range with peak PAE of 9 %. The PA chip occupies 0.256 mm2 including the pads. This chip demonstrates the highest output power from a CMOS PA in this frequency regime.
topical meeting on silicon monolithic integrated circuits in rf systems | 2016
James F. Buckwalter; Saeid Daneshgar; Jefy Jayamon; Peter M. Asbeck
We review series power combining techniques for power amplifiers that have significantly enhanced the output power and power density of millimeter-wave power amplifiers implemented in Silicon (Si) and Silicon-Germanium (SiGe) integrated circuit processes. Two of the record highpower demonstrations for Si/SiGe have included transistor stacking and sub-quarter-wavelength power combiners. A 30-GHz power amplifier implemented in 45-nm CMOS SOI demonstrates 24.5 dBm of output power with 30% PAE using four stacked FETs. A two-stage, 114-130 GHz power amplifier with stacked HBTs and sub-quarter-wavelength baluns also demonstrates a record 22 dBm output power and 254 mW/mm2 output power per unit area.
IEEE Transactions on Microwave Theory and Techniques | 2018
Narek Rostomyan; Jefy Jayamon; Peter M. Asbeck
A two-stage, high-power symmetric Doherty power amplifier (PA) at 15 GHz is presented. The PA is implemented in 45 nm CMOS silicon on insulator and achieves more than 23 dB power gain with 25.7 dBm saturated output power and 31% peak power added efficiency (PAE). The 6 dB back-off PAE is 25%, which is a 64% improvement compared to ideal class B PA back-off performance. High output power is obtained by employing four-stack multigate devices at the output stage; driver stages employ two-stack devices. A simple analog predistortion linearizer is proposed that effectively corrects the AM–AM response of the Doherty PA and extends the P1dB from 23 to 25.1 dBm. The PA also exhibits excellent AM–PM response. The amplifier has compact dimensions and occupies only 1 mm2 chip area, including pads.
radio frequency integrated circuits symposium | 2015
Gang Liu; Jefy Jayamon; James F. Buckwalter; Peter M. Asbeck
compound semiconductor integrated circuit symposium | 2015
Jefy Jayamon; James F. Buckwalter; Peter M. Asbeck
IEEE Journal of Solid-state Circuits | 2016
Jefy Jayamon; James F. Buckwalter; Peter M. Asbeck
radio frequency integrated circuits symposium | 2016
Jefy Jayamon; James F. Buckwalter; Peter M. Asbeck