James P. Libous

Power distribution networks for system-on-package: status and challenges

The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multilayer ceramic BGA

This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application-specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results.

Macromodeling of nonlinear digital I/O drivers

In this paper, a modeling technique using spline functions with finite time difference approximation is discussed for modeling moderately nonlinear digital input/output (I/O) drivers. This method takes into account both the static and the dynamic memory characteristics of the driver during modeling. Spline function with finite time difference approximation includes the previous time instances of the driver output voltage/current to capture the output dynamic characteristics of digital drivers accurately. In this paper, the speed and the accuracy of the proposed method is analyzed and compared with the radial basis function (RBF) modeling technique, for modeling different test cases. For power supply noise analysis, the proposed method has been extended to multiple ports by taking the previous time instances of the power supply voltage/current into account. The method discussed can be used to capture sensitive effects like simultaneous switching noise (SSN) and cross talk accurately when multiple drivers are switching simultaneously. A comparison study between the presented method and the transistor level driver models indicate a computational speed-up in the range of 10-40 with an error of less than 5%. For highly nonlinear drivers, a method based on recurrent artificial neural networks (RNN) is discussed.

Modeling and simulation of core switching noise for ASICs

This paper presents simulation and analysis of core switching noise for a CMOS ASIC test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.

Macro-modeling of non-linear I/O drivers using spline functions and finite time difference approximation

In this paper a modeling methodology using spline functions with finite time difference is proposed for modeling digital I/O drivers. Digital driver circuits can be accurately modeled using their static characteristics for normal excitations, but for faster excitations static characteristic models tend to lose their accuracy as the dynamic characteristics start to dominate the static characteristics. Spline function with finite time difference modeling includes previous time instances to capture dynamic characteristics for accurate modeling of digital drivers. In this paper the speed and accuracy of the proposed method is analyzed and compared with Radial Basis Function (RBF) modeling for different test cases.

I/O cell placement and electrical checking methodology for ASICs with peripheral I/Os

Optimized I/O cell placement techniques take into account electromigration (EM), IR drop, and dI/dt noise issues in the power distribution network. This paper describes fast and easy electrical checking algorithms to be used early in the design process to verify if the I/O placements meet placement guidelines, and explains the details of the I/O cell placement-related roles used by the checking tool. Use of these techniques and methods can ensure high quality ASICs.

Characterization of flip-chip CMOS ASIC simultaneous switching noise on multilayer organic and ceramic BGA/CGA packages

This paper presents the characterization of flip-chip CMOS ASIC core logic and I/O simultaneous switching noise on several types of high density multilayer organic and ceramic ball grid array (BGA) and column grid array (CGA) packages. The results of time domain simultaneous switching output noise measurements with a CMOS test chip are presented. Core logic switching noise modeling and simulation results are also discussed.

Measurement, modeling, and simulation of flip-chip CMOS ASIC simultaneous switching noise on a multi-layer ceramic BGA

This paper presents the simultaneous switching noise (SSN) measurements, modeling, and simulation of a flip-chip complementary metal-oxide-semiconductor (CMOS) application- A specific integrated circuit (ASIC) test chip on a multilayer ceramic ball grid array (CBGA) package. Technology and design features of the chip and package test vehicles are described. Time-domain noise measurement techniques and results are presented in detail. Circuit modeling and simulation methodologies are developed and validated by strong correlation between measurement and simulation results.

Modeling and simulation of core switching noise on a package and board

This paper presents simulation and analysis of core switching noise on a CMOS test vehicle. The test vehicle consists of a ceramic ball grid array (CBGA) package on a printed circuit board (PCB). The entire test vehicle has been modeled by accounting for all the plane resonances using the cavity resonator method. The models included both the on-chip and off-chip decoupling capacitors. Using both time domain and frequency domain simulations, the role of plane resonances on power supply noise for fast current edge rates has been discussed. The models have been constructed to amplify certain parts of the test vehicle during simulations.