Jan Pliva

On the design of active downconversion mixers for wireless communications on a carbon nanotube FET technology

Depletion-mode CNTFETs are being fabricated successfully with useable tolerances and compact models are now available for circuit design and engineering. This paper presents the first design study of mixers based on those devices. The impact of peculiar device features and parasitic on analog and RF circuits is discussed in detail and the cascode mixer is selected to overcome challenges specific to the available technology. Circuit performance and design for operation in the 2.4 GHz IMS band are described in detail: while consuming 182 mW and driven with −2 dBm LO power, the mixer provides 8 dB conversion gain to a 10 MHz IF frequency.

Tunable broadband integrated circuits for adaptive optical interconnects

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers.

Adaptive optical interconnects: the ADDAPT project

Existing optical networks are driven by dynamic user and application demands but operate statically at their maximum performance. Thus, optical links do not offer much adaptability and are not very energy-efficient. In this paper a novel approach of implementing performance and power adaptivity from system down to optical device, electrical circuit and transistor level is proposed. Depending on the actual data load, the number of activated link paths and individual device parameters like bandwidth, clock rate, modulation format and gain are adapted to enable lowering the components supply power. This enables flexible energy-efficient optical transmission links which pave the way for massive reductions of CO2 emission and operating costs in data center and high performance computing applications. Within the FP7 research project Adaptive Data and Power Aware Transceivers for Optical Communications (ADDAPT) dynamic high-speed energy-efficient transceiver subsystems are developed for short-range optical interconnects taking up new adaptive technologies and methods. The research of eight partners from industry, research and education spanning seven European countries includes the investigation of several adaptive control types and algorithms, the development of a full transceiver system, the design and fabrication of optical components and integrated circuits as well as the development of high-speed, low loss packaging solutions. This paper describes and discusses the idea of ADDAPT and provides an overview about the latest research results in this field.

Adaptive high-speed and ultra-low power optical interconnect for data center communications

In this paper, two basic methods for a performance and power adaptivity on system and component level in optical interconnects for data center communications are introduced and explained. The approaches are investigated in the EC FP7 project ADDAPT (Adaptive Data and Power Aware Transceivers for Optical Communications) which targets significant power savings in optical interconnects. First, a rapid link on/off switching is investigated when idle symbols are present in the data stream. For active data, a rapid on-switching in less than 20 ns at data rate of 56 Gb/s is achieved, which is almost one order of magnitude faster than in current systems. To evaluate power savings potential in links with multiple lanes, network analyses were performed and several packet statistics were investigated. As a result, up to 80% power savings can be achieved at 10% link utilization. Second, dynamic speed adaptation allows scaling down the performance of individual link system according to varying network traffic load. By this adaptive tuning, a reduction of the nominal power consumption by up to 80% is estimated when tuning down the link data rate from 56 Gb/s to 7 Gb/s.

Design of a custom standard-cell library for mixed-signal applications in 28 nm CMOS

In highly-scaled CMOS technologies, analog and digital functionality are often combined into more powerful systems. Implementation of any complex digital circuit requires digital synthesis and therefore a digital standard cell library. Absence of the digital libraries in core design kits provided by the foundries is a significant hurdle for academic institutions to design complex electronic systems. Therefore, design of a custom digital library becomes a necessary step for a successful mixed-signal design. In this paper, the design of such a custom digital library is presented. The library was designed in 28nm CMOS technology and tailored for usage in mixed-signal applications. The composition of available cells and its effect on the performance and area of the synthesized block are discussed. Moreover, different approaches to the transistor dimensioning are compared regarding design effort and performance. To verify the library and the design flow, a serial-to-parallel interface (SPI) demonstrator chip was designed, fabricated and tested. The measurement results correspond to the simulation results and were used to further improve the library and the design process. Finally, the performance of the library is compared to two other digital libraries, one of which is a state-of-the-art commercial library based on high performance 45nm silicon-on-insulator (SOI) CMOS technology. The designed library offers low leakage power and low area consumption while allowing moderate speed which is well suited for the usage in digital control blocks within the mixed-signal systems.

A fully integrated 2.6 GHz cascode class-E PA in 0.25 µm CMOS employing new bias network for stacked transistors

This work presents the design of a differential power amplifier in 0.25µm CMOS with stacked transistors operating in class-E mode. A new analytical approach is derived to design a reactive bias network so that both lower and upper switching transistors retain class-E-like voltage waveforms. By using the bias network simulations show an efficiency enhancement of more than 8 %. In measurements the amplifier achieves an output power of 21.7dBm at an drain efficiency and power added efficiency of 41.5% and 37.9% respectively at a center frequency of 2.6 GHz.