Laszlo Szilagyi

Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

This paper presents the design and analysis of a 4-level pulse-amplitude-modulation (4-PAM) 56 Gbit/s vertical-cavity surface-emitting laser (VCSEL) driver integrated circuit (IC) for short range, high speed and low power optical interconnections. An amplitude modulated signal is necessary to overcome the bottleneck of speed given by the actual VCSELs and decrease the power consumption per bit. A prototype IC is developed in a standard 130 nm BiCMOS technology. The circuit converts two single-ended input signals to a 4-level signal fed to the laser. The driver also provides the DC current and the voltage necessary to bias the VCSEL. The power dissipation of the driver is only 115 mW including both the VCSEL and the 50 Ω input single-to-differential-ended converters. To the authors knowledge this is the first 56 Gbit/s 4-PAM laser driver implemented in silicon with a power dissipation per data-rate (DR) of 2.05 mW/Gbit/s including the VCSEL making it the most power efficient, 56 Gbit/s, common cathode laser driver. The active area occupies 0.056 mm 2 . The small signal bandwidths are 49 GHz for the high and 43 GHz for the low amplitude amplification path, when the VCSEL is not connected. The bit error rate was tested electrically showing and error free connection at 28 GBaud/s.

Tunable broadband integrated circuits for adaptive optical interconnects

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers.

A 0.68 pJ/bit inductor-less optical receiver for 20 Gbps with 0.0025 mm2 area in 28 nm CMOS

This paper presents the design, electrical and optical measurements of a receiver for optical communications in 28 nm CMOS. Electrical measurements show an error-free transmission with a bit error rate (BER) of 10-12 up to 20 Gbps. Inductor-less peaking methods are used, thus the circuit is very compact. With only 0.0025 mm2, 13.6 mW power consumption, yielding 0.68 pJ/bit it is one of the smallest and most energy efficient receiver to this date for 20 Gbps data rate (DR). The receiver was bonded to a printed circuit board (PCB) and to a 14 Gbps, 850 nm photo diode. An error-free transmission over the optical link was obtained up to 17 Gbps with an input optical sensitivity of -4.3 dBm. The measured sensitivity at 15 Gbps is just -7.5 dBm and -8.4 dBm for 10 Gbps.

A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS

This paper describes a new, robust system-architecture for common-cathode (CC) vertical-cavity surface-emitting laser (VCSEL) drivers for highly-scaled CMOS technologies with low supply voltages. The concept implies converting the input signal into a current which is transferred to an amplifier built in a floating well by the level-shifter. Setting the potential of the well as high as the parasitic diode break-down voltage, a high DC bias voltage is possible for the VCSEL, several times higher than the gate-oxide break-down of CMOS technologies. The architecture is demonstrated with the design of a VCSEL driver in 80 nm CMOS with 1.2 V breakdown. The VCSEL DC bias can go as high as 4.5 V. The fabricated chip was bonded to a CC VCSEL. Electrical, optical and robustness measurements were performed. The optical eye was open until 17 Gbps at a bit-error-rate (BER) of 10-12 with only 60 mW power consumption including the VCSEL current. The driver met the electrical robustness evaluation offering a more reliable alternative to stacked CC architecture. The active area is of only 0.003 mm2, one of the smallest existing VCSEL diode drivers for this data-rate.

An inductor-less ultra-compact transimpedance amplifier for 30 Gbps in 28 nm CMOS with high energy-efficiency

A transimpedace amplifier (TIA) for optical links with data rate (DR) of up to 30 Gbps is presented. The design uses several bandwidth and gain enhancement techniques such as regulated common-gate, transimpedance boosting by current injection, transimpedance/transadmittance feedback and active inductor. The design is realized in a 28 nm CMOS technology. Since the circuit does not use any passive planar inductor or other special radio frequency component the area is only 0.4 × 10-3 mm2 and is to our knowledge the smallest TIA reported to date in the 30 Gbps DR range. The measured bandwidth is 22 GHz with a power consumption of only 2 mW resulting in an energy efficiency of 0.067 pJ/bit. The gain of the TIA is approximately 43 dBΩ with only one stage. The TIA is suitable to be integrated into complex CMOS VLSI systems as an alternative to copper-based short-distance interconnects. An output buffer for 50 Ω matching was added to the output, allowing the measurement.

Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS

The design methodology of low power current mode logic (CML) latches is described and the implementation of a D flip-flop (DFF) is presented in 28 nm CMOS technology. The DFF can work up to 22 Gbps full-rate with a bit error rate better than 10-12 and with a power consumption of only 880 μW. Since the circuit is inductor-less the area of the circuit is only 25 μm × 10 μm. As a further implementation of the CML latches a very low power static frequency divider with quadrature outputs in 28 nm is presented. It divides the clock signal up to 26 GHz and has only 880 μW power consumption. To our knowledge, with 0.034 mW/GHz, this static frequency divider has one of the best figure of merit reported to date.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm 2 , is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10 −12 at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

Area-efficient offset compensation and common-mode control circuit with switched-capacitor technique in an 18 Gbps optical receiver in 80 nm CMOS

An 18Gbps optical receiver in 80nm CMOS with a limiting amplifier employing offset compensation and common-mode control is implemented. A conventional and a proposed, 40% smaller circuit in switched-capacitor technique are measured and compared.

25 Gbit/s adaptive 3-tap FFE VCSEL driver in 28-nm CMOS for data center communications

This paper presents the design and measurement of an adaptive 3-tap feed-forward equalizer (FFE) integrated circuit (IC) manufactured in 28-nm digital bulk CMOS technology. The driver consumes only 100 mW from a single 1.5 V supply including the vertical-cavity surface-emitting laser (VCSEL) and excluding the input matching circuitry. The 50 Ω input baluns, necessary only for the measurement, are not power optimized and consume 60 mW. The driver was assembled on a printed circuit board (PCB) with DC connections and bonded to a commercially available 7.5 GHz VCSEL diode. An error-free (BER < 10−12) optical transmission with a data rate (DR) of 25 Gbit/s was achieved. It is proven that the 3-tap FFE improves the quality of the optical eye diagram at a cost of eye amplitude. When not needed, the circuitry of the FFE can be switched off saving 22.5 mW of power.

A Highly Adaptive and Energy-Efficient Optical Interconnect for On-Board Server Communications

As the global IP traffic and its demand for computation increase in a rapid and sustained manner, processor, server, and network architectures are also undergoing a considerable evolution. Two of the manifestations of this evolution are the integration of a large number of computing nodes in a single server and the interconnection of many servers via high-speed communication links. At present, however, the node-to-node communication bandwidth is one of the severest resource bottlenecks in massively parallelized applications. There is a concerted effort by the academia and the industry to achieve higher data rate by assembling multiple parallel links. This effort, however, is inherently limited by many constrains, including space. Optical interconnects, on the other hand, promise superior data rates, lower transmission losses, and less inter-channel crosstalk when compared to electrical interconnects. Development in this area promise data rates in the range of Tera bits per second per link and beyond. So far, however, little attention is given to the power adaptiveness of optical interconnects. In this paper, we present an optical interconnect concept which adjusts its power consumption in response to the change in the statistics of the incoming workload. The several components of the link have been designed and developed in hardware. Based on initial power and performance measurements of the components, a link model of our optical interconnect was created. The performance-power consumption characteristics of this model was simulated applying different workload statistics and the potential of the energy savings by the adaptivity have been evaluated. It is revealed that the power consumption of our optical interconnect reduces by up to 40% when its workload was exponentially distributed (signifying underutilisation) compared to a Weibull distribution workload (signifying full capacity workload). This study confirms the high potential for power saving in performance adaptive optical interconnects.