Mahdi Khafaji

General Time-Domain Representation of Chromatic Dispersion in Single-Mode Fibers

In this letter, an analytical method in time domain for calculation of the effect of chromatic dispersion (CD) in a single-mode fiber is presented. By using Fourier series representation of a general pulse approach, the CD effect could be obtained for arbitrary pulse shapes. As one improvement beyond the commonly used models, this work provides an analytical way to calculate the required number of taps for a finite impulse response filter equalizer without the need for empirical values. As an example, the spreading of a pulse carved by a Mach-Zehnder interferometer in an optical communication system is calculated. The novel analytical expression is in good agreement with other published results.

SFDR considerations for current steering high-speed digital to analog converters

In this paper the spurious free dynamic range (SFDR) of a current steering digital-to-analog converter (DAC) is related to the process parameters used for its implementation. It is shown that the realization of such DACs in advanced processes provides power and area reduction combined with faster signaling. However, it is very challenging to improve the SFDR at a certain given output swing and sampling frequency. It is demonstrated that the SFDR can be doubled by using an optimized cascode switch. It is also concluded that compared to MOSFET based approaches higher sampling frequencies can be achieved by bipolar transistor based DACs if the SFDR and transition frequency are fixed. The reason is the higher Early voltage of bipolar transistors.

A 6-bit Fully Binary Digital-to-Analog Converter in 0.25-

This paper presents an approach to implement a high-speed binary weighted digital-to-analog converter (DAC). A different current switching mechanism is proposed that improves the dynamic performance of binary weighted DACs. Circuit simulation shows an improvement of the rise (fall) time mismatch by a factor of 2 over the conventional structure. It is shown that in a conventional high-speed binary DAC implemented with differential pairs, the spurious-free dynamic range (SFDR) can be degraded by nearly 6 dB due to the different rise (fall) times of the current switches. Using the proposed current switches, a fully binary weighted DAC with nominal resolution of 6 bit has been fabricated in 0.25-μm SiGe technology. The measured SFDR is higher than 30.1 dBc up to 5.9-GHz input signal with a 13.4-GHz clock. The DAC can provide 1.1-V peak-to-peak differential output swing over 50 Ω while dissipating 1050 mW. Full-scale 20%-80% fall time and 2% settling time are measured below 18 and 45 ps, respectively.

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This paper presents an accurate yet compact model for vertical cavity surface emitting lasers (VCSEL), which can be extracted from simple DC and small-signal electro-optical measurements. Since VCSELs are the bottleneck of high-speed electro-optical transceivers, the model is essential in the design of high-speed laser drivers. VCSEL rate equations are used to describe the electrical to optical conversion in the laser, while non-linear parasitcs are modelling the VCSEL interface. The model is applied to a commercially available VCSEL and there is an excellent agreement between the simulated and measured eye diagrams at different data rates and bias currents.

SiGe BiCMOS for Optical Communications

This article presents a 20 GHz, 12-bit pipeline accumulator with a reduced number of registers, suitable for direct digital synthesiser (DDS) applications. The accumulator is implemented in the IHP SG25H1 (0.25 μm) SiGe:C technology featuring heterojunction bipolar transistors (HBTs) with F t / F max of 180/220 GHz. The accumulator architecture omits the pre-skewing registers of the pipeline, thereby lowering both power consumption and circuit complexity. Some limitations to this design are discussed and the necessary equations for determining the phase jump encountered each time the control word (synthesised frequency) is changed are presented. For many applications employing signal processing after detection, this phase shift can then be corrected for. Compared to a full pipeline architecture (omitting the input circuitry for the most significant bit, as is customary for such designs), the implemented 12-bit accumulator reduces the number of registers by 55% and the power by approximately 32%, while obtaining the highest clock frequency for SiGe:C accumulators intended for DDS applications.

A compact electro-optical VCSEL model for high-speed IC design

This paper describes the design of an energy-efficient vertical-cavity surface-emitting laser (VCSEL) driver circuit implemented in a 130 nm SiGe BiCMOS technology. The driver features a 3-tap feed-forward equalizer where positive and negative peaks are added to the main signal to compensate for the low-pass characteristic of VCSELs. The circuit is also able to generate asymmetric pre-emphasis to counteract the VCSEL nonlinearity. Bonded to an 18 GHz VCSEL, the driver can reach an error-free (bit error rate < 10−12) optical data rate of 50 Gb/s with an horizontal eye opening better than 0.2 unit interval using a 22 GHz photoreceiver without equalization, retiming, and limiting amplifier at the receiver side. At 48 Gb/s, the horizontal eye opening is 0.5 unit interval. The circuit dissipates only 190 mW from a dual supply of 2.5 and 3.3 V, including the VCSEL power. To the best of the authors’ knowledge, this is the fastest common-cathode VCSEL driver with lowest power consumption for data rates higher than 35 Gb/s. Thanks to the active delay line and the application of vertical inductor, the driver is very compact with an active area of only 0.036 mm2 including the inductor.

Twelve-bit 20-GHz reduced size pipeline accumulator in 0.25 μm SiGe:C technology for direct digital synthesiser applications

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers.

A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver

Existing optical networks are driven by dynamic user and application demands but operate statically at their maximum performance. Thus, optical links do not offer much adaptability and are not very energy-efficient. In this paper a novel approach of implementing performance and power adaptivity from system down to optical device, electrical circuit and transistor level is proposed. Depending on the actual data load, the number of activated link paths and individual device parameters like bandwidth, clock rate, modulation format and gain are adapted to enable lowering the components supply power. This enables flexible energy-efficient optical transmission links which pave the way for massive reductions of CO2 emission and operating costs in data center and high performance computing applications. Within the FP7 research project Adaptive Data and Power Aware Transceivers for Optical Communications (ADDAPT) dynamic high-speed energy-efficient transceiver subsystems are developed for short-range optical interconnects taking up new adaptive technologies and methods. The research of eight partners from industry, research and education spanning seven European countries includes the investigation of several adaptive control types and algorithms, the development of a full transceiver system, the design and fabrication of optical components and integrated circuits as well as the development of high-speed, low loss packaging solutions. This paper describes and discusses the idea of ADDAPT and provides an overview about the latest research results in this field.

Tunable broadband integrated circuits for adaptive optical interconnects

This paper demonstrates a 34 Gbit/s 4:1 multiplexer with 200 mW power dissipation in a 0.25-μm SiGe process. A multiphase clock architecture at half-rate clock is chosen to reduce the power dissipation. In addition, stability issues caused by the capacitively loaded clock driver are studied and a solution is proposed with a suitable compensation circuit. Measurement results are presented as well. The output signals yield open eye diagrams at the highest available test rate of 34 Gbit/s, while presenting rise and fall times below 12 ps.

Adaptive optical interconnects: the ADDAPT project

An 80 Gbps 215-1 pseudo-random bit sequence (PRBS) generator offering a unique feature of two programmable channels is presented. It is possible to select either a replica of the full rate stream, two parallel streams at half the rate, or a combination of external and internal pattern to the output. This flexibility makes the design suitable for generating proper test signal for both binary and 4-PAM (pulse-amplitude-modulation) communication systems. While the longer sequence in this design adds to the complexity, the energy per bit is comparable with the state-of-the-art designs. Notably for the clock drivers, as one of the bottlenecks of a PRBS generator, an open-collector structure with distributed loading is studied and optimized for very low power operation. The design features a clock divider and zero detection circuit as well. The circuit was fabricated in a 130 nm SiGe BiCMOS process (300/500 GHz fr/fmax).