Guido Belfiore

170 GHz SiGe-BiCMOS Loss-Compensated Distributed Amplifier

This paper presents a travelling-wave amplifier (TWA) for wideband applications implemented in a 0.13 µm SiGe BiCMOS technology (ft = 300 GHz, fmax = 500 GHz). The gain cell employed in the TWA is designed to compensate the transmission-line- losses at high frequencies in order to extend the bandwidth as well as the gain bandwidth product (GBP). A gain of 10 dB and a 3-dB bandwidth of 170 GHz are measured for the fabricated TWA. The chip has a chip area of 0.38 mm² and a power consumption of 108 mW. Compared against the state of the art, the presented design achieves the highest reported GBP per area and power consumption.

New design approach of vertical inductors for high-frequency integrated circuits

This paper presents a new method for the design of inductors in high-frequency integrated circuits. In order to increase the inductance per unit of area more than one metal layer is used and the spiral inductor is oriented in the vertical instead of the horizontal plane. The inductor is designed in 130 nm BiCMOS technology using five metal layers. Simulations were performed via Sonnet 3D EM software. The inductance at low frequencies was verified with the Greenhouse method using Grover formulas. Good agreement between simulations and analytical calculations was found when the inductance length and metal width was changed. As a first proof of concept, an inductor of 340 pH with self-resonance frequency of 51.7 GHz and a quality factor of 3.14 at 26 GHz was designed, which is well suited for peaking purposes. The designed inductor shows an inductance per unit of area of 377 nH/mm2. This is a significant improvement compared to planar inductors.

Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

This paper presents the design and analysis of a 4-level pulse-amplitude-modulation (4-PAM) 56 Gbit/s vertical-cavity surface-emitting laser (VCSEL) driver integrated circuit (IC) for short range, high speed and low power optical interconnections. An amplitude modulated signal is necessary to overcome the bottleneck of speed given by the actual VCSELs and decrease the power consumption per bit. A prototype IC is developed in a standard 130 nm BiCMOS technology. The circuit converts two single-ended input signals to a 4-level signal fed to the laser. The driver also provides the DC current and the voltage necessary to bias the VCSEL. The power dissipation of the driver is only 115 mW including both the VCSEL and the 50 Ω input single-to-differential-ended converters. To the authors knowledge this is the first 56 Gbit/s 4-PAM laser driver implemented in silicon with a power dissipation per data-rate (DR) of 2.05 mW/Gbit/s including the VCSEL making it the most power efficient, 56 Gbit/s, common cathode laser driver. The active area occupies 0.056 mm 2 . The small signal bandwidths are 49 GHz for the high and 43 GHz for the low amplitude amplification path, when the VCSEL is not connected. The bit error rate was tested electrically showing and error free connection at 28 GBaud/s.

A compact electro-optical VCSEL model for high-speed IC design

This paper presents an accurate yet compact model for vertical cavity surface emitting lasers (VCSEL), which can be extracted from simple DC and small-signal electro-optical measurements. Since VCSELs are the bottleneck of high-speed electro-optical transceivers, the model is essential in the design of high-speed laser drivers. VCSEL rate equations are used to describe the electrical to optical conversion in the laser, while non-linear parasitcs are modelling the VCSEL interface. The model is applied to a commercially available VCSEL and there is an excellent agreement between the simulated and measured eye diagrams at different data rates and bias currents.

The effect of strong equalization in high-speed VCSEL-based optical communications up to 48 Gbit/s

In this paper the design of a VCSEL driver with strong equalization is presented. Unlike other published works the pre-emphasis provided from the proposed driver and the output voltage swing are independently tunable up to the saturation of the output stage (~700 mVpp in 50 Ω load environment). The driver is designed in 130 nm SiGe BiCMOS technology. Thanks to the various bandwidth extension techniques, the electrical data-rate at which the driver can operate is higher than 50 Gbit/s. A wide open optical eye diagram is measured at 48 Gbit/s with a 20 GHz VCSEL. The driver and the VCSEL consume only 188 mW from a dual voltage supply of 2.5 and 3.4 V. To the best of the authors knowledge 3.9 mW/(Gbit/s) is the highest reported energy-efficiency for a common-cathode VCSEL driver with data-rate higher than 40 Gbit/s. Moreover an open eye at 48 Gbit/s is the fastest reported for a common cathode VCSEL driver without pre-emphasis in the receiver.

A 50 Gb/s 190 mW Asymmetric 3-Tap FFE VCSEL Driver

This paper describes the design of an energy-efficient vertical-cavity surface-emitting laser (VCSEL) driver circuit implemented in a 130 nm SiGe BiCMOS technology. The driver features a 3-tap feed-forward equalizer where positive and negative peaks are added to the main signal to compensate for the low-pass characteristic of VCSELs. The circuit is also able to generate asymmetric pre-emphasis to counteract the VCSEL nonlinearity. Bonded to an 18 GHz VCSEL, the driver can reach an error-free (bit error rate < 10−12) optical data rate of 50 Gb/s with an horizontal eye opening better than 0.2 unit interval using a 22 GHz photoreceiver without equalization, retiming, and limiting amplifier at the receiver side. At 48 Gb/s, the horizontal eye opening is 0.5 unit interval. The circuit dissipates only 190 mW from a dual supply of 2.5 and 3.3 V, including the VCSEL power. To the best of the authors’ knowledge, this is the fastest common-cathode VCSEL driver with lowest power consumption for data rates higher than 35 Gb/s. Thanks to the active delay line and the application of vertical inductor, the driver is very compact with an active area of only 0.036 mm2 including the inductor.

Tunable broadband integrated circuits for adaptive optical interconnects

To accommodate the growing demand on higher speeds, low latencies and low energy consumption, the interconnections within and between data centers are supposed to be implemented as optical fiber and waveguide interconnects in future. Optical fiber interconnects provide several advantages over their electrical counterparts as they enable higher bandwidth densities and lower losses at high frequencies over distances longer than few centimeters. However, nowadays optical fiber interconnects are usually not very energy-efficient. The systems in optical networks are mostly optimized for running at their peak performance to transmit the information with the highest available error-free data rate. But the work load of a processor system and hence of an optical link is not constant and varies over time due to the demand of the running applications and users. Therefore, optical interconnects consume the same high power at all times even if lower performance is required. In this paper a new method for the tuning of optical interconnects for on-board and board-to-board optical communication is described. In this way the performance of the transceiver systems of the link is adapted to the present transmission workload and link requirements. If for example lower data rates are required, the bandwidth and therefore the power consumption of the systems can be reduced. This tuning is enabled by the integrated circuitry of the optical link. Different methods for such an adaptive tuning are described and several practical examples are reviewed. By using adaptive bandwidth reduction in the circuits, more than 50 % of the consumed power can be saved. These savings can result in tremendous reductions of the carbon footprint and of the operating costs produced by data centers.

A high-voltage DC bias architecture implementation in a 17 Gbps low-power common-cathode VCSEL driver in 80 nm CMOS

This paper describes a new, robust system-architecture for common-cathode (CC) vertical-cavity surface-emitting laser (VCSEL) drivers for highly-scaled CMOS technologies with low supply voltages. The concept implies converting the input signal into a current which is transferred to an amplifier built in a floating well by the level-shifter. Setting the potential of the well as high as the parasitic diode break-down voltage, a high DC bias voltage is possible for the VCSEL, several times higher than the gate-oxide break-down of CMOS technologies. The architecture is demonstrated with the design of a VCSEL driver in 80 nm CMOS with 1.2 V breakdown. The VCSEL DC bias can go as high as 4.5 V. The fabricated chip was bonded to a CC VCSEL. Electrical, optical and robustness measurements were performed. The optical eye was open until 17 Gbps at a bit-error-rate (BER) of 10-12 with only 60 mW power consumption including the VCSEL current. The driver met the electrical robustness evaluation offering a more reliable alternative to stacked CC architecture. The active area is of only 0.003 mm2, one of the smallest existing VCSEL diode drivers for this data-rate.

Low power inductor-less CML latch and frequency divider for full-rate 20 Gbps in 28-nm CMOS

The design methodology of low power current mode logic (CML) latches is described and the implementation of a D flip-flop (DFF) is presented in 28 nm CMOS technology. The DFF can work up to 22 Gbps full-rate with a bit error rate better than 10-12 and with a power consumption of only 880 μW. Since the circuit is inductor-less the area of the circuit is only 25 μm × 10 μm. As a further implementation of the CML latches a very low power static frequency divider with quadrature outputs in 28 nm is presented. It divides the clock signal up to 26 GHz and has only 880 μW power consumption. To our knowledge, with 0.034 mW/GHz, this static frequency divider has one of the best figure of merit reported to date.

20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm 2 , is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10 −12 at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.